XC3S1000L Xilinx Corp., XC3S1000L Datasheet - Page 2

• Manufacturer Part Number: XC3S1000L
• Description: Spartan-3l Low Power Fpga Family
• Manufacturer: Xilinx Corp.

Spartan-3L Low Power FPGA Family
Architectural Overview
The Spartan-3L family architecture consists of five funda-
mental programmable functional elements:
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Configuration
Spartan-3L FPGAs are programmed by loading configura-
tion data into robust static memory cells that collectively
control all functional elements and routing resources.
Before powering on the FPGA, configuration data is stored
externally in a PROM or some other nonvolatile medium
either on or off the board. After applying power, the configu-
ration data is written to the FPGA using any of five different
modes: Master Parallel, Slave Parallel, Master Serial, Slave
2
Configurable
RAM-based Look-Up Tables (LUTs) to implement logic
and storage elements that can be used as flip-flops or
latches. CLBs can be programmed to perform a wide
variety of logical functions as well as to store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Twenty-six different signal standards,
including eight high-performance differential standards,
are available, as shown in
(DDR) registers are included. The Digitally Controlled
Impedance (DCI) feature provides automatic on-chip
terminations, simplifying board designs.
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
Logic
Notes:
1.
The two additional block RAM columns of the XC3S4000L devices are shown
with dashed lines.
Blocks
Table
2. Double Data-Rate
Figure 1: Spartan-3L Family Architecture
(CLBs)
contain
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These elements are organized as shown in
of IOBs surrounds a regular array of CLBs. The XC3S1000L
and XC3S1500L have two columns of block RAM. The
XC3S4000L has four RAM columns. Each column is made
up of several 18Kbit RAM blocks; each block is associated
with a dedicated multiplier. The DCMs are positioned at the
ends of the outer block RAM columns.
The Spartan-3L family features a rich network of traces that
interconnect all five functional elements, transmitting sig-
nals among them. Each functional element has an associ-
ated switch matrix that permits multiple connections to the
routing.
Serial and Boundary Scan (JTAG). The Master and Slave
Parallel modes use an 8-bit wide SelectMAP port.
The recommended memory for storing the configuration
data is the low-cost Xilinx Platform Flash PROM family,
which includes the XCF00S PROMs for serial configuration
and the higher density XCF00P PROMs for parallel or serial
configuration.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
DS099-1_01_032703
DS313 (v1.2) April 18, 2008
Product Specification
Figure
1. A ring
R