XC3S1000L Xilinx Corp., XC3S1000L Datasheet - Page 8

• Manufacturer Part Number: XC3S1000L
• Description: Spartan-3l Low Power Fpga Family
• Manufacturer: Xilinx Corp.

Spartan-3L Low Power FPGA Family
Figure 4, page 7
ing the Hibernate mode.
The steps for entering the Hibernate mode are as follows:
1. Pull the PROG_B pin Low to put all I/Os into a
2. The FPGA drives the INIT_B and DONE pins Low.
3. External switches are used to turn off the V
4. The FPGA is now in the Hibernate mode. As long as the
The steps for exiting the Hibernate mode are as follows:
1. Before FPGA initialization can begin, it is necessary to
2. Reapply power to all rails that were switched off. Apply
3. After logic initialization, the FPGA releases the
4. When configuration is complete, the FPGA enters the
5. The FPGA is now ready for user operation.
8
high-impedance state.
V
described above, it is possible to switch off V
given bank in cases where the I/O pins of the
associated bank are Low or disabled throughout the
Hibernation period.
FPGA is kept in this state, power consumption rests at
the lowest possible level.
deassert PROG_B to a High logic level. The rising
transition must occur after turning all three power
supplies back on.
power in any sequence.
open-drain INIT_B signal. Now that INIT_B is High,
reconfiguration can begin.
Startup phase, asserts DONE, and enables the I/Os,
according to how the BitGen options are set.
CCAUX
rails. This action resets the FPGA. As
shows the waveforms for entering and exit-
CCINT
CCO
www.xilinx.com
for a
and
Special Considerations
In the Hibernate mode, whenever one of the V
turned off, keep the voltage on the I/O pins of the associated
bank below 0.5V. As an alternative, it is possible to disable
any signals that an external device might apply to the bank’s
I/O pins. Voltages higher than 0.5V can turn on the power
diodes. Keeping the diode off prevents “reverse current”
from flowing into the V
V
BUSY, and D0-D3. V
pose inputs: RDWR_B, CS_B, and D4-D7. The V
of Banks 0, 1, 4, and 5 power the Global Clock inputs
GCLK0 - GCLK1, GCLK2 - GCLK3, GCLK4 - GCLK5, and
GCLK6 - GCLK7, respectively. In the Hibernate mode, if any
of these rails is turned off, do not apply voltages in excess of
0.5V to any of the associated Dual-Purpose pins. This mea-
sure keeps the power diodes off.
V
HSWAP_EN, M0-M2, CCLK (in Slave mode), TDI, TCK,
and TMS. Once in the Hibernate mode, do not apply volt-
ages in excess of 0.5V to any of these pins. In this case,
keeping the power diode off prevents a “reverse current”
from flowing into the V
V
Master mode), and TDO. Once in the Hibernate mode, the
states of these pins are undefined.
V
BUSY/DOUT. Whenever V
the Hibernation period, the state of this pin is undefined.
CCO
CCAUX
CCAUX
CCO
Bank 4 powers the Dual-Purpose inputs: INIT_B, DIN,
Bank
powers the Dedicated outputs: DONE, CCLK (in
powers
4
powers
CCO
the
CCO
CCAUX
Bank 5 powers the other Dual-Pur-
Dedicated
CCO
rail.
the
rail.
Bank 4 is turned off during
DS313 (v1.2) April 18, 2008
Dual-Purpose
Product Specification
inputs:
CCO
PROG_B,
CCO
outputs:
rails is
lines
R