TSS463C ATMEL Corporation, TSS463C Datasheet - Page 14

• Manufacturer Part Number: TSS463C
• Description: Van Data Link Controller With Serial Interface
• Manufacturer: ATMEL Corporation

VAN Protocol
Line Interface
Figure 10. CSMA/CD Arbritration
14
TSS463C
On Bus: DATA
Node c: TxD
Node a: TxD
Node b: TxD
There are three line inputs and one line output available on the TSS463C. that of the
three inputs to use is either programmable by software or automatically selected by a
diagnosis system.
The diagnosis system continuously monitors the data received through the three inputs,
and compares it with each other and the selected bitrate. It then chooses the most reli-
able input according to the results.
The data on the line is encoded according to the VAN standard ISO/11519-3. This
means that the TSS463C is using a two level signal having a recessive (1) and a domi-
nant (0) state. Furthermore, due to the simple medium used, all data transmitted on the
bus is also received simultaneously.
The VAN protocol is hence a CSMA/CD (Carrier Sense Multiple Access Collision Detec-
tion) protocol, allowing for continuous bitwise arbitration of the bus, and non-destructive
(for the higher priority messa ge) collision detection.
In addition to the VAN specification there is also a pulsed coding of the dominant and
recessive states. This mode is intended to be used with an optical or radio link. In this
mode the dominant state for the transmitter is a low pulse (2x prescaled clocks at the
beginning of the bit) and the recessive state is just a high level. When receiving in this
mode it is not the state of the signal itself that is decoded, but the edges. Also, reception
is imposed on the RxD0 input, and the diagnosis system does not operate correctly.
In addition, in this mode there is an internal loopback in the circuit since optical trans-
ceivers are not able to receive the signal that they transmit.
R
D
R
D
R
D
R
D
R: Recessive Level
D: Dominant Level
Arbitration field
1
2
Node c loses the arbitration
Node c releases the bus
3
Node a loses the arbitration
Node a releases the bus
Node b wins the arbitration
7601B–AUTO–02/06