TSS463C ATMEL Corporation, TSS463C Datasheet - Page 30

• Manufacturer Part Number: TSS463C
• Description: Van Data Link Controller With Serial Interface
• Manufacturer: ATMEL Corporation

ETIP: Enable Transmission In
Progress
ESDC: Enable System
Diagnosis Clock
GRES: General Reset
SLEEP: Sleep command
IDLE: Idle command
ACTI: Activate command
30
Command Register (0x03)
TSS463C
The Transmission In Progress (TIP) tells the diagnosis system to enable transmission
diagnosis.
One: Enable TIP generation
Zero: Disable TIP generation.
The Synchronous Diagnosis Clock (SDC) controls the cycle time of the synchronous
diagnosis.
One: Enable SDC divider.
Zero: Disable SDC divider.
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•
•
The Reset circuit command bit performs, if set, exactly as if the external reset pin was
asserted. This command bit has its own auto-reset circuitry.
One: Reset active
Zero: Reset inactive
(Section “Sleep Command”, page 51). If the user sets the Sleep bit, the circuit will enter
sleep mode. When the circuit is in sleep mode, all non-user registers are setup to mini-
mize power consumption. Read/write accesses to the TSS463C via the SPI/SCI
interface are impossible, the oscillator is stopped.
To exit from this mode the user must apply either an hardware reset (external RESET
pin) either an asynchronous software reset (via the SPI/SCI interface).
One: Sleep active
Zero: Sleep inactive
(Section “Idle and Activate Commands”, page 51). If the user sets the Idle bit, the circuit
will enter idle mode. In idle mode the oscillator will operate, but the TSS463C will not
transmit or receive anything on the bus, and the TxD output will be in tri-state
One: Idle active
Zero: Idle inactive
(Section “Idle and Activate Commands”, page 51). The Activate command will put the
circuit in the active mode, i.e it will transmit and receive normally on the bus. When the
circuit is in activate mode the TxD tri-state output is enabled.
One: Activate active
Zero: Activate inactive
GRES
Write only register.
Reserved: Bit 1, 2. These bits must not be set by the user; a zero must always be
written to these bit.
If the circuit is operating at low bitrates, there might be a considerable delay
between the writing of this register and the performing of the actual command (worst
case 6 timeslots). The user is therefore recommended to verify, by reading the Line
Status Register (0x04), that the commands have been performed.
7
SLEEP
6
IDLE
5
ACTI
4
REAR
3
2
0
1
0
7601B–AUTO–02/06
MSDC
0