HT45R37V Holtek Semiconductor Inc., HT45R37V Datasheet - Page 38

• Manufacturer Part Number: HT45R37V
• Description: C/r-f Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

conversion cycle will be initiated. When the START bit is
brought from low to high but not low again, the EOCB bit
in the ADCR register will be set high and the analog to
digital converter will be reset. It is the START bit that is
used to control the overall on/off operation of the internal
analog to digital converter.
The EOCB bit in the ADCR register is used to indicate
when the analog to digital conversion process is com-
plete. This bit will be automatically cleared to zero by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the inter-
rupts are enabled, an appropriate internal interrupt sig-
nal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D inter-
nal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOCB bit in the ADCR register to check whether
it has been cleared as an alternative method of detect-
ing the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates
from the system clock f
ratio, the value of which is determined by the ADCS2,
ADCS1 and ADCS0 bits in the ACSR register.
Controlling the on/off function of the A/D converter cir-
cuitry is implemented using the ADONB bit in the ACSR
Rev. 1.00
SYS
, is first divided by a division
A/D Converter Control Register - ADCR
®
®
38
register and the value of the PCR bits in the ADCR reg-
ister. Both the ADONB bit must cleared to zero and the
value of the PCR bits must have a non-zero value for the
A/D converter to be enabled.
Although the A/D clock source is determined by the sys-
tem clock f
there are some limitations on the maximum A/D clock
source speed that can be selected. As the minimum value
of permissible A/D clock period, t
taken for system clock speeds in excess of 4MHz. For
system clock speeds in excess of 4MHz, the ADCS2,
ADCS1 and ADCS0 bits should not be set to 000 . Doing
so will give A/D clock periods that are less than the mini-
mum A/D clock period which may result in inaccurate A/D
conversion values. Refer to the following table for exam-
ples, where values marked with an asterisk * show where,
depending upon the device, special care must be taken,
as the values may be less than the specified minimum A/D
Clock Period.
PCR
> 0
> 0
0
SYS
, and by bits ADCS2, ADCS1 and ADCS0,
ADONB
0
1
x
AD
, is 0.5 s, care must be
October 20, 2009
HT45R37V
A/D
Off
On
Off