HT45R37V Holtek Semiconductor Inc., HT45R37V Datasheet - Page 59

• Manufacturer Part Number: HT45R37V
• Description: C/r-f Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Timer/Event Counter Interrupt
For a Timer/Event Counter 0 or Timer/Event Counter 1
interrupt to occur, the global interrupt enable bit, EMI,
and the corresponding timer interrupt enable bit, ET0I or
ET1I must first be set. An actual Timer/Event Counter in-
terrupt will take place when the Timer/Event Counter re-
quest flag, T0F or T1F is set, a situation that will occur
when the Timer/Event Counter overflows. When the in-
terrupt is enabled, the stack is not full and a Timer/Event
Counter overflow occurs, a subroutine call to the timer
interrupt vector at location 0CH or 10C, will take place.
When the interrupt is serviced, the timer interrupt re-
quest flag, T0F or T1F, will be automatically reset and
the EMI bit will be automatically cleared to disable other
interrupts.
A/D Interrupt
The A/D Interrupt is contained within the Multi-function
Interrupt 1.
For an A/D Interrupt to be generated, the global interrupt
enable bit, EMI, A/D Interrupt enable bit, EADI, and
Multi-function Interrupt 1 enable bit, EMF1I, must first be
set. An actual A/D Interrupt will take place when the A/D
Interrupt request flag, ADF, is set, a situation that will oc-
cur when the A/D conversion process has finished.
When the interrupt is enabled, the stack is not full and
the A/D conversion process has ended, a subroutine
call to the Multi-function Interrupt 1 vector at
location18H, will take place. When the A/D Interrupt is
serviced, the EMI bit will be cleared to disable other in-
terrupts, however only the MF1F interrupt request flag
will be reset. As the ADF flag will not be automatically re-
set, it has to be cleared by the application program.
Multi-function Interrupts
Additional interrupts known as the Multi-function inter-
rupts are provided. Unlike the other interrupts, these in-
terrupts have no independent source, but rather are
formed from other existing interrupt sources, namely the
A/D Converter interrupt, Time Base interrupt, Real Time
Clock interrupt, SIM Interface Interrupt and the C/R to F
interrupt.
Rev. 1.00
Interrupt Active Edge Register - INTEDGE
59
For a Multi-function interrupt to occur, the global interrupt
enable bit, EMI, and the Multi-function interrupt enable
bit, EMF0I or EMF1I, must first be set. An actual
Multi-function interrupt will take place when the
Multi-function interrupt request flag, MF0F, or MF1F is
set. This will occur when either a Time Base overflow, a
Real Time Clock overflow, an A/D conversion completion,
C/R to F converter counters, Timer A or Timer B overflow
or SIM data transfer or I2C address match occurs. When
the interrupt is enabled and the stack is not full, and either
one of the interrupts contained within the Multi-function
interrupts occurs, a subroutine call to one of the
Multi-function interrupt vector at location 014H or 018H
will take place. When the interrupt is serviced, the
Multi-Function request flag, MF0F or MF1F, will be auto-
matically reset and the EMI bit will be automatically
cleared to disable other interrupts. However, it must be
noted that the request flags from the original source of the
Multi-function interrupt, namely the Time-Base interrupt,
Real Time Clock interrupt, A/D Converter interrupt, SIM
Interface or C/R to F converter Interrupt will not be auto-
matically reset and must be manually reset by the appli-
cation program.
SPI/I
The SPI/I
Multi-function Interrupt 0.
For an /I
bit, EMI, the corresponding interrupt enable bit, ESIM
and Multi-function Interrupt 0 enable bit, EMF0I, must be
first set. An actual SPI/I
the SPI/I
set, a situation that will occur when a byte of data has
been transmitted or received by the SPI/I
when an I
is enabled, the stack is not full and a byte of data has
been transmitted or received by the SPI/I
an I
Multi-function Interrupt 0 vector at location 14H, will take
place. When the interrupt is serviced, the Multi-function
Interrupt 0 request flag, MF0F, will be automatically re-
set and the EMI bit will be automatically cleared to dis-
2
C address match occurs, a subroutine call to the
2
C Interface Interrupt
2
2
C interrupt to occur, the global interrupt enable
C reset function interface request flag, SIMF, is
2
2
C interface Interrupt is contained within the
C address match occurs. When the interrupt
2
C interrupt will take place when
October 20, 2009
HT45R37V
2
2
C interface or
C interface or