HT45R37V Holtek Semiconductor Inc., HT45R37V Datasheet - Page 60

• Manufacturer Part Number: HT45R37V
• Description: C/r-f Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

able other interrupts. As the SIMF flag will not be
automatically reset it has to be cleared by the applica-
tion program.
C/R to F Converter Interrupt
The C/R to converter Interrupt is contained within the
Multi-function Interrupt 0.
For a C/R to F converter interrupt to be generated, the
global interrupt enable bit, EMI, the corresponding inter-
rupt enable bit, ERCOCI and Multi-function Interrupt 0
enable bit, EMF0I, must be first set. An actual C/R to F
converter interrupt will take place when the C/R to F
converter interrupt request flag, RCOCF, is set, a situa-
tion that will occur when one of the C/R to F converter
counters, Timer A or Timer B, overflows. When the inter-
rupt is enabled, the stack is not full and a C/R to F con-
verter counter overflow occurs, a subroutine call to the
Multi-function Interrupt 0 vector at location 14H, will take
place. When the interrupt is serviced, the Multi-function
Interrupt 0 request flag, MF0F, will be automatically re-
set and the EMI bit will be automatically cleared to dis-
able other interrupts. As the RCOCF flag will not be
automatically reset it has to be cleared by the applica-
tion program.
Real Time Clock Interrupt
The Real Time Clock Interrupt is contained within the
Multi-function Interrupt 1.
For a Real Time Clock interrupt to be generated, the
global interrupt enable bit, EMI , Real Time Clock inter-
rupt enable bit, ERTI, and Multi-function Interrupt 1 en-
able bit, EMF1I, must first be set. An actual Real Time
Clock interrupt will take place when the Real Time Clock
request flag, RTF, is set, a situation that will occur when
the Real Time Clock overflows. When the interrupt is en-
abled, the stack is not full and the Real Time Clock over-
flows, a subroutine call to the Multi-function Interrupt 1
vector at location18H, will take place. When the Real
Time Clock interrupt is serviced, the EMI bit will be
cleared to disable other interrupts, however only the
MF1F interrupt request flag will be reset. As the RTF
Rev. 1.00
Time Base Interrupt
RTC Interrupt
60
flag will not be automatically reset, it has to be cleared
by the application program.
Similar in operation to the Time Base interrupt, the pur-
pose of the RTC interrupt is also to provide an interrupt
signal at fixed time periods. The RTC interrupt clock
source originates from the internal clock source f
f
ratio of which is selected by programming the appropri-
ate bits in the RTCC register to obtain longer RTC inter-
rupt periods whose value ranges from 2
clock source that generates f
RTC interrupt period, can originate from three different
sources, the 32768Hz oscillator, 32K_INT oscillator or
the System oscillator/4, the choice of which is determine
by the f
Note that the RTC interrupt period is controlled by both
configuration options and an internal register RTCC. A
configuration option selects the source clock for the in-
ternal clock f
RT0 select the division ratio. Note that the actual divi-
sion ratio can be programmed from 2
Essentially operating as a programmable timer, when
the Real Time Clock overflows it will set a Real Time
Clock interrupt flag which will in turn generate an Inter-
rupt request via the Multi-function Interrupt 1 vector.
Time Base Interrupt
The Time Base Interrupt is contained within the
Multi-function Interrupt 1.
For a Time Base Interrupt to be generated, the global in-
terrupt enable bit, EMI,Time Base Interrupt enable bit,
ETBI, and Multi-function Interrupt enable 1 bit, EMF1I,
must first be set. An actual Time Base Interrupt will take
place when the Time Base Interrupt request flag, TBF, is
set, a situation that will occur when the Time Base over-
flows. When the interrupt is enabled, the stack is not full
and the Time Base overflows, a subroutine call to the
Multi-function Interrupt 1 vector at location18H, will take
place. When the Time Base Interrupt is serviced, the
EMI bit will be cleared to disable other interrupts, how-
S
input clock first passes through a divider, the division
S
clock source configuration option.
S
, and the RTCC register bits RT2, RT1 and
S
, which in turn controls the
8
October 20, 2009
HT45R37V
to 2
8
/f
S
15
~2
.
15
/f
S
S
. This
. The