HT45R37V Holtek Semiconductor Inc., HT45R37V Datasheet - Page 70

• Manufacturer Part Number: HT45R37V
• Description: C/r-f Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Power Down Mode and Wake-up
Executing the HALT Instruction
If the device is running in the Normal Mode and the
HALT instruction is executed then the system clock will
stop to conserve power. Depending upon the condition
of the IDLEN bit in the CLKMOD register, the system
will enter either the Sleep or Idle Mode. In these Modes
the system clock will stop running to conserve power,
however as either the 32K_INT or the external 32KHz
oscillator may continue to operate, certain internal func-
tions may remain operational.
When the HALT instruction is executed in the Normal
Mode, the following will occur:
Standby Current Considerations
As the main reason for entering the Sleep or Idle Mode
is to keep the current consumption of the MCU to as low
a value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimized. Special atten-
tion must be made to the I/O pins on the device. All
high-impedance input pins must be connected to either
a fixed high or low level as any floating input pins could
create internal oscillations and result in increased cur-
rent consumption. This also applies to devices which
have different package types, as there may be
unbonbed pins, which must either be setup as outputs
or if setup as inputs must have pull-high resistors
connected. Care must also be taken with the loads,
which are connected to I/O pins, which are setup as out-
puts. These should be placed in a condition in which
minimum current is drawn or connected only to external
circuits that do not draw current, such as other CMOS
inputs. Also note that additional standby current will also
be required if the configuration options have enabled the
Watchdog Timer internal oscillator.
Rev. 1.00
The system oscillator will stop running.
The system will enter either the Sleep or Idle Mode.
The Data Memory contents and registers will maintain
their present condition.
The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the
32K_INT or external 32KHz oscillator. The WDT will
stop if its clock source originates from the system
clock.
The I/O ports will maintain their present condition.
In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
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Wake-up
After the system enters the Sleep or Idle Mode, it can be
woken up from one of various sources listed as follows:
If the system is woken up by an external reset, the de-
vice will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the ac-
tual source of the wake-up can be determined by exam-
ining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the HALT
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
Each pin on Port A can be setup, using the PAWU regis-
ter, to permit a negative transition on the pin to wake-up
the system. When a Port A pin wake-up occurs, the pro-
gram will resume execution at the instruction following
the HALT instruction.
If the system is woken up by an interrupt, then two possi-
ble situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume exe-
cution at the instruction following the HALT instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be ser-
viced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to 1 be-
fore entering the Sleep or Idle Mode, the wake-up func-
tion of the related interrupt will be disabled.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to t
system clock periods will be required before normal sys-
tem operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt sub-
routine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the HALT instruction, this
will be executed immediately after the t
period delay has ended.
An external reset
An external falling edge on Port A
A system interrupt
A WDT overflow
October 20, 2009
HT45R37V
SST
system clock
SST