DSPIC33FJ32MC202 Microchip Technology Inc., DSPIC33FJ32MC202 Datasheet
DSPIC33FJ32MC202
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DSPIC33FJ32MC202 Summary of contents
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... Microchip Technology Inc. dsPIC33FJ16MC304 Data Sheet High-Performance, 16-bit Microcontrollers Preliminary DS70283B ...
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... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary , K L logo, microID, MPLAB, PIC DSCs code hopping ® ® © 2007 Microchip Technology Inc. ...
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... FIFO on each capture • Output Compare ( channels): - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM mode © 2007 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Interrupt Controller: • 5-cycle latency • 118 interrupt vectors • available interrupt sources • ...
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... IrDA encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS Packaging: • 28-pin SDIP/SOIC/QFN-S • 44-pin QFN/TQFP Note: See the device variant tables for exact peripheral features per device. Preliminary © 2007 Microchip Technology Inc. ...
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... PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Controller Families Program Flash Device Pins Memory (Kbyte) (Kbyte) dsPIC33FJ32MC202 28 32 ...
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... CAP DDCORE TDO/PWM2L1/SDA1/RP9/CN21/RB9 11 18 TCK/PWM2H1/SCL1/RP8/CN22/RB8 INT0/RP7/CN23/RB7 PGC3/EMUC3/ASCL1/RP6/CN24/RB6 PWM1L2/RP13/CN13/RB13 1 21 PWM1H2/RP12/CN14/RB12 2 20 PGEC2/EMUC2/TMS/PWM1L3/RP11/CN15/RB11 3 19 dsPIC33FJ32MC202 PGED2/EMUD2/TDI/PWM1H3/RP10/CN16/RB10 CAP TDO/PWM2L1/SDA1/RP9/CN21/RB9 Preliminary /V DDCORE © 2007 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) 44-Pin QFN 22 AN4/RP2/CN6/RB2 23 AN5/RP3/CN7/RB3 24 AN6/RP16/CN8/RC0 25 AN7/RP17/CN9/RC1 26 AN8/RP18/CN10/RC2 OSCI/CLKI/CN30/RA2 30 OSCO/CLKO/CN29/RA3 31 TDO/RA8 32 SOSCI/RP4/CN1/RB4 33 34 © 2007 Microchip Technology Inc PWM1L2/RP13/CN13/RB13 11 PWM1H2/RP12/CN14/RB12 10 PGEC2/EMUC2/PWM1L3/RP11/CN15/RB11 9 PGED2/EMUD2/PWM1H3/RP10/CN16/RB10 8 V CAP 7 dsPIC33FJ32MC204 dsPIC33FJ16MC304 RP25/CN19/RC9 5 RP24/CN20/RC8 4 PWM2L1/RP23/CN17/RC7 3 PWM2H1/RP22/CN18/RC6 ...
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... Pin Diagrams (Continued) 44-Pin TQFP AN4/RP2/CN6/RB2 23 24 AN5/RP3/CN7/RB3 25 AN6/RP16/CN8/RC0 26 AN7/RP17/CN9/RC1 27 AN8/RP18/CN10/RC2 OSCI/CLKI/CN30/RA2 31 OSCO/CLKO/CN29/RA3 32 TDO/RA8 33 SOSCI/RP4/CN1/RB4 DS70283B-page 6 11 PWM1L2/RP13/CN13/RB13 10 PWM1H2/RP12/CN14/RB12 9 PGEC2/EMUC2/PWM1L3/RP11/CN15/RB11 8 PGED2/EMUD2/PWM1H3/RP10/CN16/RB10 CAP DDCORE dsPIC33FJ32MC204 dsPIC33FJ16MC304 5 RP25/CN19/RC9 4 RP24/CN20/RC8 3 PWM2L1/RP23/CN17/RC7 2 PWM2H1/RP22/CN18/RC6 1 SDA1/RP9/CN21/RB9 Preliminary © 2007 Microchip Technology Inc. ...
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... Table of Contents dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Product Families.................................................................................................. 3 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU............................................................................................................................................................................................ 13 3.0 Memory Organization ................................................................................................................................................................. 25 4.0 Flash Program Memory.............................................................................................................................................................. 51 5.0 Resets ....................................................................................................................................................................................... 57 6.0 Interrupt Controller ..................................................................................................................................................................... 63 7.0 Oscillator Configuration .............................................................................................................................................................. 95 8.0 Power-Saving Features............................................................................................................................................................ 105 9.0 I/O Ports ................................................................................................................................................................................... 107 10.0 Timer1 ...................................................................................................................................................................................... 133 11.0 Timer2/3 feature ...................................................................................................................................................................... 135 12.0 Input Capture............................................................................................................................................................................ 141 13.0 Output Compare....................................................................................................................................................................... 143 14.0 Motor Control PWM Module ..................................................................................................................................................... 147 15 ...
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... NOTES: DS70283B-page 8 Preliminary © 2007 Microchip Technology Inc. ...
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... The dsPIC33F devices contain extensive Digital Signal Processor (DSP) functionality with a high performance 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ32MC202/ 204 and dsPIC33FJ16MC304 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. ...
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... FIGURE 1-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCH PCL PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode & Control Control Signals to Various Blocks Power-up ...
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... CMOS Legend: CMOS = CMOS compatible input or output; Analog = Analog input ST = Schmitt Trigger input with CMOS levels Output Input Power © 2007 Microchip Technology Inc. Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. ...
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... Positive supply for analog modules. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Preliminary © 2007 Microchip Technology Inc. ...
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... As a result, three parameter instructions can be supported, allowing operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 2-1, and the programmer’s model for the dsPIC33FJ32MC202/ 204 and dsPIC33FJ16MC304 is shown in Figure 2-2. © 2007 Microchip Technology Inc. 2.1 ...
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... Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0). FIGURE 2-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller ...
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... FIGURE 2-2: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG OAB SAB DA SRH © 2007 Microchip Technology Inc. D15 D0 W0/WREG W1 W2 ...
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... IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70283B-page 16 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2007 Microchip Technology Inc. ...
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... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). © 2007 Microchip Technology Inc. (2) Preliminary DS70283B-page 17 ...
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... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70283B-page 18 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) Preliminary R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2007 Microchip Technology Inc. ...
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... Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note 1: This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2007 Microchip Technology Inc. Preliminary DS70283B-page 19 ...
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... The dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources can be used concurrently by the same instruction (e ...
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... MAC MAC MOVSAC MPY MPY MPY.N MSC FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2007 Microchip Technology Inc. Algebraic Operation – y – y change – – 40-bit Accumulator A ...
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... Overflow Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1 register are set (refer to Section 6.0 “Interrupt Controller”). This allows the user applica- tion to take immediate action, for example, to correct system gain. Preliminary and the SAT<A:B> © 2007 Microchip Technology Inc. ...
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... The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported: © 2007 Microchip Technology Inc. • W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction. • ...
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... DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is pre- sented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts. Preliminary © 2007 Microchip Technology Inc. ...
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... This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 3-1: PROGRAM MEMORY MAPS FOR dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 DEVICES dsPIC33FJ32MC202/204 0x000000 GOTO Instruction 0x000002 ...
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... Byte (read as ‘0’) DS70283B-page 26 3.1.2 INTERRUPT AND TRAP VECTORS All dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code ...
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... The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. ...
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... FIGURE 3-3: DATA MEMORY MAP FOR dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 DEVICES WITH 2 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x0BFF 0x0001 2 Kbyte SRAM Space 0x0FFF 0x1001 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70283B-page 28 LSB ...
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... All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. © 2007 Microchip Technology Inc. Preliminary DS70283B-page 29 ...
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TABLE 3-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32MC202 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — CN30IE CN29IE — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A — CN30PUE CN29PUE — Legend unknown value on Reset, — ...
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TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — ...
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TABLE 3-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 3-8: 6-OUTPUT PWM1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P1TCON 01C0 PTEN — PTSIDL — P1TMR 01C2 PTDIR P1TPER 01C4 — P1SECMP 01C6 SEVTDIR PWM1CON1 01C8 — — — — PWM1CON2 01CA ...
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TABLE 3-10: QEI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Name — QEICON 01E0 CNTERR QEISIDL INDX DFLTCON 01E2 — — — — POSCNT 01E4 MAXCNT 01E6 Legend uninitialized ...
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... TABLE 3-14: ADC1 REGISTER MAP FOR dsPIC33FJ32MC202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD 031A ...
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TABLE 3-15: ADC1 REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ...
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... RPINR21 06AA — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-17: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32MC202 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — ...
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... RPOR12 06D8 — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-19: PORTA REGISTER MAP FOR dsPIC33FJ32MC202 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name — — — — TRISA ...
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TABLE 3-21: PORTB REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 PORTB 02CA RB15 RB14 RB13 RB12 LATB 02CC LATB15 LATB14 LATB13 LATB12 ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 ...
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TABLE 3-24: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR — NVMKEY 0766 — — — — Legend unknown value on Reset, — = unimplemented, read as ...
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... SOFTWARE STACK In addition to its use as a working register, the W15 register in the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 devices is also used as a soft- ware Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 3-4 ...
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... Not all instructions support all the address- ing modes given above. Individual instruc- tions may support different subsets of these addressing modes. © 2007 Microchip Technology Inc. Description The address of the file register is specified explicitly. The contents of a register are accessed directly. ...
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... Modulo Addressing Modulo Addressing mode is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code typical in many DSP algorithms. ...
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... The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment © 2007 Microchip Technology Inc. If the length of a bit-reversed buffer the last ‘N’ bits of the data buffer start address must be zeros. ...
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... FIGURE 3-6: BIT-REVERSED ADDRESS EXAMPLE b15 b14 b13 b12 b11 b10 b9 b8 b15 b14 b13 b12 b11 b10 b9 b8 TABLE 3-27: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address ...
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... To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the dsPIC33FJ32MC202/ 204 and dsPIC33FJ16MC304 architecture provides two methods by which program space can be accessed during operation: • ...
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... FIGURE 3-7: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) Program Counter (2) Table Operations (1) Program Space Visibility (Remapping) User/Configuration Space Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2007 Microchip Technology Inc Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...
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... READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H) ...
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... Run-Time Self-Programming (RTSP) ICSP allows a dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGC1/ PGD1, PGC2/PGD2 or PGC3/PGD3), and three other ...
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... RTSP Operation The dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions time, and to program one row or one word at a time. Table 23-12 shows typical erase and program- ming times ...
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... No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2007 Microchip Technology Inc. (1) U-0 U-0 — — (1) U-0 R/W-0 — ...
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... Bit is set bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits DS70283B-page 54 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2007 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary © 2007 Microchip Technology Inc. ...
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... RESETS Note: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.micro- chip.com) for the latest dsPIC33F Family Reference Manual sections ...
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... If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70283B-page 58 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... SWR (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) Note: All Reset flag bits may be set or cleared by the user software. © 2007 Microchip Technology Inc. (1) Setting Event Trap conflict event Illegal opcode or uninitialized W register access Configuration mismatch MCLR Reset ...
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... Preliminary FSCM Notes Delay — FSCM FSCM LOCK FSCM — FSCM FSCM LOCK FSCM — 3 — 3 — 3 — 3 — 3 — 3 © 2007 Microchip Technology Inc. ...
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... FRC oscillator and the user application can switch to the desired crystal oscillator in the Trap Service Routine. © 2007 Microchip Technology Inc. 5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources When the system clock source is provided by a crystal ...
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... NOTES: DS70283B-page 62 Preliminary © 2007 Microchip Technology Inc. ...
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... Reference Manual sections. The dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 interrupt controller reduces the numerous peripheral interrupt request signals to a sin- gle interrupt request signal to the dsPIC33FJ32MC202/ 204 and dsPIC33FJ16MC304 CPU. It has the following features: • processor exceptions and software traps • 7 user-selectable priority levels • ...
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... FIGURE 6-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 Interrupt Vector 52 ...
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... Microchip Technology Inc. AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – Input Capture 2 0x000120 OC2 – ...
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... IVT Address AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Preliminary Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved © 2007 Microchip Technology Inc. ...
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... Interrupt Control and Status Registers dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices implement a total of 22 registers for the inter- rupt controller: • INTCON1 • INTCON2 • IFSx • IECx • IPCx • INTTREG 6.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources ...
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... U = Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) R/W-0 R/W-0 US EDT R/W-0 R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set © 2007 Microchip Technology Inc. ...
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... MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...
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... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70283B-page 70 Preliminary © 2007 Microchip Technology Inc. ...
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... Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — ...
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... OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70283B-page 72 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. Preliminary DS70283B-page 73 ...
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... SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70283B-page 74 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... QEIIF: QEI Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 PWM1IF: PWM1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. U-0 U-0 R/W-0 — — QEIIF U-0 U-0 U-0 — ...
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... Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ DS70283B-page 76 U-0 U-0 R/W-0 — — FLTA2IF U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 U-0 PWM2IF — bit 8 U-0 U-0 U1EIF — bit Bit is unknown ...
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... Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — ...
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... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70283B-page 78 Preliminary © 2007 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 ...
Page 82
... Interrupt request enabled 0 = Interrupt request not enabled bit 8-0 Unimplemented: Read as ‘0’ DS70283B-page 80 U-0 U-0 R/W-0 — — QEIIE U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 U-0 PWM1IE — bit 8 U-0 U-0 — — bit Bit is unknown ...
Page 83
... PWM2IE: PWM2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. U-0 U-0 R/W-0 — — FLA2IE U-0 U-0 U-0 — ...
Page 84
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70283B-page 82 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 85
... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 U-1 — — Unimplemented bit, read as ‘0’ ...
Page 86
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70283B-page 84 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 87
... Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. U-0 U-0 R/W-1 — — — R/W-0 U-0 R/W-1 — ...
Page 88
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70283B-page 86 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 89
... Interrupt source is disabled bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ...
Page 90
... Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70283B-page 88 U-0 U-0 U-1 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 91
... Unimplemented: Read as ‘0’ bit 6-4 PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ...
Page 92
... Bit is cleared U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 93
... Interrupt source is disabled bit 6-4 PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. U-0 U-0 R/W-0 — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ...
Page 94
... Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70283B-page 92 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 95
... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be ter- minated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2007 Microchip Technology Inc. 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 96
... NOTES: DS70283B-page 94 Preliminary © 2007 Microchip Technology Inc. ...
Page 97
... Microchip web site (www.micro- chip.com) for the latest dsPIC33F Family Reference Manual sections. The dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 oscillator system provides: • External and internal oscillator options as clock sources FIGURE 7-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator OSCO S3 OSCI S1 FRC Oscillator TUN<5:0> ...
Page 98
... The output of the oscillator (or the output of the PLL if a PLL mode has been selected) F generate the device instruction clock (F defines the operating speed of the device, and speeds dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 architecture. Instruction execution speed or device operating frequency, F EQUATION 7-1: 7.1.3 The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation ...
Page 99
... MHz, which is within the 100-200 MHz ranged needed. • If PLLPOST<1:0> then This provides a Fosc of 160 MHz. The resultant device operating speed is 80 MIPS. FIGURE 7-2: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) TABLE 7-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode ...
Page 100
... FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ DS70283B-page 98 R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-y R/W-y NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
Page 101
... REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete © 2007 Microchip Technology Inc. Preliminary DS70283B-page 99 ...
Page 102
... Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. DS70283B-page 100 R/W-0 R/W-0 R/W-1 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 103
... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 104
... Center frequency -0.375% (7.345 MHz) • • • 100001 = Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz) DS70283B-page 102 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 105
... Clock Switching Operation Applications are free to switch among any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices have a safeguard lock built into the switch process. Note: ...
Page 106
... NOTES: DS70283B-page 104 Preliminary © 2007 Microchip Technology Inc. ...
Page 107
... Put the device into IDLE mode © 2007 Microchip Technology Inc. 8.2 Instruction-Based Power-Saving Modes dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 and devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution ...
Page 108
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). Preliminary © 2007 Microchip Technology Inc. are eight possible ® DSC variant. If the ...
Page 109
... I/O PORTS Note: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.micro- chip.com) for the latest dsPIC33F Family Reference Manual sections ...
Page 110
... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Preliminary dsPIC33FJ32MC202/204 and © 2007 Microchip Technology Inc. ...
Page 111
... These modules include I A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC). © 2007 Microchip Technology Inc. Remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In ...
Page 112
... QEB RPINR14 INDX RPINR15 U1RX RPINR18 U1CTS RPINR18 SDI1 RPINR20 SCK1 RPINR20 SS1 RPINR21 Preliminary (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> FLTA1R<4:0> FLTA2R<4:0> QEAR<4:0> QEBR<4:0> INDXR<4:0> U1RXR<4:0> U1CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> © 2007 Microchip Technology Inc. ...
Page 113
... SCK1OUT SS1OUT OC1 OC2 UPDN © 2007 Microchip Technology Inc. value of the bit field corresponds to one of the periph- erals, and that peripheral’s output is mapped to the pin (see Table 9-2 and Figure 9-3). The list of peripherals for output mapping also includes a null value of 00000 because of the mapping tech- nique ...
Page 114
... The unlock sequence must be executed as an assem- bly-language routine, in the same manner as changes to the oscillator configuration, because the unlock sequence is timing-critical. If the bulk of the application is written another high-level language, the unlock sequence should be performed by writing inline assembler. Preliminary © 2007 Microchip Technology Inc. ...
Page 115
... Example 9-2 shows a configuration for bidirectional communication with flow control using UART1. The following input and output functions are used: • Input Functions: U1RX, U1CTS • Output Functions: U1TX, U1RTS © 2007 Microchip Technology Inc. EXAMPLE 9-2: CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS ...
Page 116
... Peripheral Pin Select Registers The dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 family of devices implement 21 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (13) • Output Remappable Peripheral Registers (8) Note: Input and Output Register values can only be changed if OSCCON[IOLOCK See Section 9.4.4.1 “Control Register Lock” for a specific command sequence. ...
Page 117
... INTR2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 118
... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70283B-page 116 R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 R/W-1 T2CKR<4:0> Bit is unknown © 2007 Microchip Technology Inc. bit 8 bit 0 ...
Page 119
... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS ...
Page 120
... IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding pin RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70283B-page 118 R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 IC8R<4:0> bit 8 R/W-1 R/W-1 R/W-1 IC7R<4:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 121
... FLTA1R<4:0>: Assign PWM1 Fault (FLTA1) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 122
... Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70283B-page 120 U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 FLTA2R<4:0> Bit is unknown © 2007 Microchip Technology Inc. bit 8 bit 0 ...
Page 123
... Unimplemented: Read as ‘0’ bit 4-0 QEB1R<4:0>: Assign A(QEA) to the corresponding pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary ...
Page 124
... Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70283B-page 122 U-0 U-0 — — R/W-1 R/W-1 INDX1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 125
... U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS ...
Page 126
... SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70283B-page 124 R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 R/W-1 SDI1R<4:0> Bit is unknown © 2007 Microchip Technology Inc. bit 8 bit 0 ...
Page 127
... SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 128
... DS70283B-page 126 R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 R/W-0 R/W-0 RP0R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 RP3R<4:0> R/W-0 R/W-0 R/W-0 RP2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 129
... RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 R/W-0 R/W-0 RP4R< ...
Page 130
... DS70283B-page 128 R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 R/W-0 R/W-0 RP8R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 RP11R<4:0> R/W-0 R/W-0 R/W-0 RP10R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 131
... RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 R/W-0 R/W-0 RP12R< ...
Page 132
... DS70283B-page 130 R/W-0 R/W-0 R/W-0 RP17R<4:0> R/W-0 R/W-0 R/W-0 RP16R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 RP19R<4:0> R/W-0 R/W-0 R/W-0 RP18R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 133
... RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP21R<4:0> R/W-0 R/W-0 R/W-0 RP20R< ...
Page 134
... Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 9-2 for peripheral function numbers) DS70283B-page 132 R/W-0 R/W-0 R/W-0 RP25R<4:0> R/W-0 R/W-0 R/W-0 RP24R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 135
... TIMER1 Note: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.micro- chip.com) for the latest dsPIC33F Family Reference Manual sections ...
Page 136
... External clock from pin T1CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ DS70283B-page 134 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 137
... TIMER2/3 FEATURE Note: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.micro- chip.com) for the latest dsPIC33F Family Reference Manual sections ...
Page 138
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70283B-page 136 (1) 1x Gate 01 Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2007 Microchip Technology Inc. ...
Page 139
... FIGURE 11-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2007 Microchip Technology Inc. 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TCS TGATE DS70283B-page 137 ...
Page 140
... In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. DS70283B-page 138 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 141
... External clock from pin T3CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer functions are set through T2CON. © 2007 Microchip Technology Inc. U-0 U-0 (1) — — R/W-0 U-0 (1) — ...
Page 142
... NOTES: DS70283B-page 140 Preliminary © 2007 Microchip Technology Inc. ...
Page 143
... Reference Manual sections. The input capture module is useful in applications requiring frequency (period) and pulse measurement. The dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 devices support up to eight input capture channels. The input capture module captures the 16-bit value of the selected Time Base register when an event occurs at the ICx pin ...
Page 144
... DS70283B-page 142 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 145
... OUTPUT COMPARE Note: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.micro- chip.com) for the latest dsPIC33F Family Reference Manual sections ...
Page 146
... A PRy value of N will produce a PWM period time base count cycles. For example, a value of 7 written into the PRy register will yield a period consisting of eight time base cycles. PWM DUTY CYCLE ) CY PWM bits ( MHz and a Timer2 CY © 2007 Microchip Technology Inc. ...
Page 147
... Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through 8. 2: OCFA pin controls OC1-OC2 channels. 3: TMR2/TMR3 can be selected via OCTSEL (OCxCON<3>) bit. © 2007 Microchip Technology Inc 122 Hz 977 Hz 1 ...
Page 148
... Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled DS70283B-page 146 U-0 U-0 U-0 — — — R-0 HC R/W-0 R/W-0 OCFLT OCTSEL HS = Set in Hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 OCM<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 149
... Microchip web site (www.micro- chip.com) for the latest dsPIC33F Family Reference Manual sections. The dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 device supports up to two dedi- cated Pulse Width Modulation (PWM) modules. The PWM1 module is a 6-channel PWM generator, and the PWM2 module is a 2-channel PWM generator. ...
Page 150
... Channel 2 Dead-Time #2 PWM Generator Channel 1 Dead-Time #1 Special Event Postscaler SEVTDIR PTDIR Preliminary PWM1H3 Generator and PWM1L3 Override Logic PWM1H2 Generator and Output PWM1L2 Override Logic Driver Block PWM1H1 Generator and PWM1L1 Override Logic FLTA1 Special Event Trigger © 2007 Microchip Technology Inc. ...
Page 151
... P2FLTACON P2OVDCON P2TMR Comparator P2TPER P2TPER Buffer P2TCON Comparator P2SECMP PWM Time Base © 2007 Microchip Technology Inc. PWM Enable and Mode SFRs Dead-Time Control SFRs Fault Pin Control SFRs PWM Manual Control SFR PWM Generator # 1 P2DC1Buffer P2DC1 Comparator Channel 1 Dead-Time ...
Page 152
... The postscaler selection bits can be used in this mode of the timer to reduce the frequency of interrupt events. TCON SFR. X Preliminary TMR register is X TPER register occurs X TMR register matches the P TPER reg- X TPER register occurs. The X TPER reg- X © 2007 Microchip Technology Inc. ...
Page 153
... X • A write to the P TCON register X • Any device Reset The P TMR register is not cleared when P X ten. © 2007 Microchip Technology Inc. 14.4 PWM Period P TPER is a 15-bit register used to set the counting X TMR register X period for the PWM time base. P buffered register. The P loaded into the P • ...
Page 154
... PxTMR register matches the value in the PxTPER register. The contents of the duty cycle buffers are automatically loaded into the Duty PTMR Cycle registers when the PWM time base is disabled Value (PTEN = 0). Preliminary © 2007 Microchip Technology Inc. ...
Page 155
... Duty Cycle Generator PWMxH PWMxL Time Selected by DTSxA bit ( © 2007 Microchip Technology Inc. Complementary mode is selected for each PWM pin pair by clearing the appropriate PMODx bit in the PWMxCON1 SFR. The PWM I/O pins are set to Complementary mode by default upon a device Reset. ...
Page 156
... COMPLEMENTARY OUTPUT MODE When a PWMxL pin is driven active via the PxOVD- CON register, the output signal is forced to be the com- plement of the corresponding PWMxH pin in the pair. Dead-time insertion is still performed when PWM channels are overridden manually. Preliminary © 2007 Microchip Technology Inc. ...
Page 157
... There is one Fault pin (FLTAx) associated with the PWM module. When asserted, this pin can optionally drive each of the PWM I/O pins to a defined state. © 2007 Microchip Technology Inc. 14.14.1 FAULT PIN ENABLE BITS The PxFLTACON SFR have four control bits that deter- mine whether a particular pair of PWM I/O pins controlled by the Fault input pin ...
Page 158
... The PxTCON SFR contains a PTSIDL control bit. This bit determines if the PWM module will continue to operate or stop when the device enters Idle mode. If PTSIDL = 0, the module will continue to operate. If PTSIDL = 1, the module will stop operation as long as the CPU remains in Idle mode. Preliminary © 2007 Microchip Technology Inc. ...
Page 159
... PWM time base operates in a Continuous Up/Down Count mode with interrupts for double PWM updates 10 = PWM time base operates in a Continuous Up/Down Count mode 01 = PWM time base operates in Single Pulse mode 00 = PWM time base operates in a Free-Running mode © 2007 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 160
... PTPER<14:0>: PWM Time Base Period Value bits DS70283B-page 158 R/W-0 R/W-0 R/W-0 PTMR<14:8> R/W-0 R/W-0 R/W-0 PTMR<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PTPER<14:8> R/W-0 R/W-0 R/W-0 PTPER<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 161
... A Special Event Trigger will occur when the PWM time base is counting downward Special Event Trigger will occur when the PWM time base is counting upward bit 14-0 SEVTCMP<14:0>: Special Event Compare Value bits Note 1: SEVTDIR is compared with PTDIR (P 2: PxSECMP<14:0> is compared with P © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (2) SEVTCMP<14:8> R/W-0 R/W-0 ...
Page 162
... PWM2 supports only 1 PWM I/O pin pair. DS70283B-page 160 (2) U-0 U-0 — — PMOD3 R/W-1 U-0 (1) (1) PEN1H — PEN3L U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary R/W-0 R/W-0 R/W-0 PMOD2 PMOD1 bit 8 R/W-1 R/W-1 R/W-1 (1) (1) (1) PEN2L PEN1L bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 163
... Output overrides via the PxOVDCON register occur on next T bit 0 UDIS: PWM Update Disable bit 1 = Updates from Duty Cycle and Period Buffer registers are disabled 0 = Updates from Duty Cycle and Period Buffer registers are enabled © 2007 Microchip Technology Inc. U-0 R/W-0 R/W-0 — SEVOPS<3:0> ...
Page 164
... Clock period for Dead-Time Unit bit 5-0 DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits DS70283B-page 162 R/W-0 R/W-0 R/W-0 DTB<5:0> R/W-0 R/W-0 R/W-0 DTA<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 165
... Dead time provided from Unit A bit 0 DTS1I: Dead-Time Select for PWM1 Signal Going Inactive bit 1 = Dead time provided from Unit Dead time provided from Unit A Note 1: PWM2 supports only 1 PWM I/O pin pair. © 2007 Microchip Technology Inc. (1) U-0 U-0 U-0 — — — ...
Page 166
... PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A Note 1: PWM2 supports only 1 PWM I/O pin pair. DS70283B-page 164 (1) R/W-0 R/W-0 R/W-0 FAOV3L FAOV2H FAOV2L U-0 U-0 R/W-0 — — FAEN3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 FAOV1H FAOV1L bit 8 R/W-0 R/W-0 FAEN2 FAEN1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 167
... POUTxH<3:1>:POUTxL<3:1>: PWM Manual Output bits 1 = PWMx I/O pin is driven active when the corresponding POVDxH:POVDxL bit is cleared 0 = PWMx I/O pin is driven inactive when the corresponding POVDxH:POVDxL bit is cleared Note 1: PWM2 supports only 1 PWM I/O pin pair. © 2007 Microchip Technology Inc. (1) R/W-1 R/W-1 R/W-1 POVD3L POVD2H ...
Page 168
... PDC2<15:0>: PWM Duty Cycle #2 Value bits DS70283B-page 166 R/W-0 R/W-0 R/W-0 PDC1<15:8> R/W-0 R/W-0 R/W-0 PDC1<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PDC2<15:8> R/W-0 R/W-0 R/W-0 PDC2<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 169
... REGISTER 14-13: P1DC3: PWM DUTY CYCLE REGISTER 3 R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC3<15:0>: PWM Duty Cycle #3 Value bits © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PDC3<15:8> R/W-0 R/W-0 R/W-0 PDC3<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 ...
Page 170
... NOTES: DS70283B-page 168 Preliminary © 2007 Microchip Technology Inc. ...
Page 171
... QUADRATURE ENCODER INTERFACE (QEI) MODULE Note: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.micro- chip ...
Page 172
... Position counter reset by detection of index pulse, QEIM<2:0> = 110. • Position counter reset by match with MAXCNT, QEIM<2:0> = 111. The x4 Measurement mode provides for finer resolu- tion data (more position counts) for determining motor position. Preliminary COUNT DIRECTION STATUS © 2007 Microchip Technology Inc. ...
Page 173
... Timer register. When UPDN = 1, the timer counts up. When UPDN = 0, the timer counts down. © 2007 Microchip Technology Inc. In addition, control bit UPDN_SRC, (in QEICON<0>), determines whether the timer count direction state is based on the logic state written into the UPDN control/ status bit (QEICON< ...
Page 174
... Note: The POSCNT accesses,. However, reading the register in Byte mode can result in partially updated values in subsequent reads. Either use Word mode reads/writes, or ensure that the counter is not counting during Byte operations. Preliminary © 2007 Microchip Technology Inc. register allows byte ...
Page 175
... Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin Position Counter Direction Status Output Disabled (Normal I/O pin operation) bit 5 TQGATE: Timer Gated Time Accumulation Enable bit 1 = Timer gated time accumulation enabled 0 = Timer gated time accumulation disabled © 2007 Microchip Technology Inc. R-0 R/W-0 R/W-0 INDEX UPDN ...
Page 176
... UPDN_SRC: Position Counter Direction Selection Control bit 1 = QEB pin state defines position counter direction 0 = Control/Status bit, UPDN (QEICON<11>), defines timer counter (POSCNT) direction Note: When configured for QEI mode, control bit is a ‘don’t care’. DS70283B-page 174 Preliminary © 2007 Microchip Technology Inc. ...
Page 177
... Clock Divide 110 = 1:128 Clock Divide 101 = 1:64 Clock Divide 100 = 1:32 Clock Divide 011 = 1:16 Clock Divide 010 = 1:4 Clock Divide 001 = 1:2 Clock Divide 000 = 1:1 Clock Divide bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. U-0 U-0 R/W-0 — — IMV<2:0> U-0 U-0 — — ...
Page 178
... NOTES: DS70283B-page 176 Preliminary © 2007 Microchip Technology Inc. ...
Page 179
... SERIAL PERIPHERAL INTERFACE (SPI) Note: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.micro- chip ...
Page 180
... SPI error conditions. 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer SPIxTXB Write SPIxBUF 16 Internal Data Bus Preliminary registers with MSTEN 1:1/4/16/64 Primary F CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2007 Microchip Technology Inc. ...
Page 181
... User application must write transmit data to or read received data from SPIxBUF. The SPIxTXB and SPIxRXB regis- ters are memory mapped to SPIxBUF. FIGURE 16-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM dsPIC33F FIGURE 16-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM dsPIC33F © 2007 Microchip Technology Inc. PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer SDIx SDOx LSb ...
Page 182
... Preliminary PROCESSOR 2 PROCESSOR 2 4:1 6:1 8:1 10000 6666.67 5000 2500 1666.67 1250 625 416.67 312.50 156.25 104.17 78.125 1250 833 625 313 208 156 © 2007 Microchip Technology Inc. ...
Page 183
... SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB © 2007 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 184
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). DS70283B-page 182 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE<2:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 PPRE<1:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 185
... PPRE<1:0>: Primary Prescale bits (Master mode Primary prescale 1 Primary prescale 4 Primary prescale 16 Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). © 2007 Microchip Technology Inc. Preliminary DS70283B-page 183 ...
Page 186
... Unimplemented: This bit must not be set to ‘1’ by the user application. DS70283B-page 184 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 U-0 FRMDLY — bit Bit is unknown ...
Page 187
... C) Note: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.micro- chip.com) for the latest dsPIC33F Family Reference Manual sections ...
Page 188
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2007 Microchip Technology Inc. ...
Page 189
... Least Significant 8 bits of I2CxADD, as specified in the 10-bit addressing protocol. 2 TABLE 17-1: 7-BIT I C™ SLAVE ADDRESSES SUPPORTED BY dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 0x00 General call address or Start byte 0x01-0x03 Reserved 0x04-0x07 Hs mode Master codes ...
Page 190
... C module has limited peripheral pin select func- tionality. When the ALTI2C bit in the FPOR configura- tion register is set to ‘1’, I pins. When ALTI2C bit is ‘0’, I ASCLx pins. Preliminary © 2007 Microchip Technology Inc port to its Idle state module uses SDAx/SLCx 2 ...
Page 191
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2007 Microchip Technology Inc. R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 192
... Start condition not in progress DS70283B-page 190 2 C master, applicable during master receive) C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte master master) Preliminary 2 C master) © 2007 Microchip Technology Inc. ...
Page 193
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2007 Microchip Technology Inc. U-0 U-0 — — R/C-0 HSC ...
Page 194
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70283B-page 192 2 C slave device address byte. Preliminary © 2007 Microchip Technology Inc. ...
Page 195
... Unimplemented: Read as ‘0’ bit 9-0 AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2007 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 196
... NOTES: DS70283B-page 194 Preliminary © 2007 Microchip Technology Inc. ...
Page 197
... The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules avail- able in the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 device family. The UART is a full- duplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also ...
Page 198
... Desired Baud Rate Preliminary UART BAUD RATE WITH BRGH = Baud Rate = 4 • (BRGx + BRGx = – • Baud Rate F denotes the instruction cycle clock CY frequency (F /2). OSC © 2007 Microchip Technology Inc ...
Page 199
... Write 0x55 to UxTXREG, which loads the Sync charac- ter into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2007 Microchip Technology Inc. 18.5 Receiving in 8-bit or 9-bit Data Mode 1. Set up the UART (as described in Section 18.2 “ ...
Page 200
... This feature is only available for the 16x BRG mode (BRGH = 0). DS70283B-page 198 MODE REGISTER x R/W-0 R/W-0 U-0 (1) IREN RTSMD R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 — UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2007 Microchip Technology Inc. ...