DSPIC33FJ32MC202 Microchip Technology Inc., DSPIC33FJ32MC202 Datasheet - Page 190

• Manufacturer Part Number: DSPIC33FJ32MC202
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

17.11 Slope Control
The I
and SCLx signals for Fast mode (400 kHz). The control
bit, DISSLW, enables the user application to disable
slew rate control if desired. It is necessary to disable
the slew rate control for 1 MHz mode.
17.12 Clock Arbitration
Clock arbitration occurs when the master deasserts the
SCLx pin (SCLx allowed to float high) during any
receive, transmit or Restart/Stop condition. When the
SCLx pin is allowed to float high, the Baud Rate Gen-
erator (BRG) is suspended from counting until the
SCLx pin is actually sampled high. When the SCLx pin
is sampled high, the BRG is reloaded with the contents
of I2CxBRG and begins counting. This process
ensures that the SCLx high time will always be at least
one BRG rollover count in the event that the clock is
held low by an external device.
DS70283B-page 188
2
C standard requires slope control on the SDAx
Preliminary
17.13 Multi-Master Communication, Bus
Multi-Master mode support is achieved by bus
arbitration. When the master outputs address/data bits
onto the SDAx pin, arbitration takes place when the
master outputs a ‘1’ on SDAx by letting SDAx float high
while another master asserts a ‘0’. When the SCLx pin
floats high, data should be stable. If the expected data
on SDAx is a ‘1’ and the data sampled on the
SDAx pin = 0, then a bus collision has taken place. The
master sets the I
resets the master portion of the I
17.14 Peripheral Pin Select Limitations
The I
tionality. When the ALTI2C bit in the FPOR configura-
tion register is set to ‘1’, I
pins. When ALTI2C bit is ‘0’, I
ASCLx pins.
2
C module has limited peripheral pin select func-
Collision and Bus Arbitration
2
C master events interrupt flag and
© 2007 Microchip Technology Inc.
2
C module uses SDAx/SLCx
2
C module uses ASDAx/
2
C port to its Idle state.