DSPIC30F4012 Microchip Technology Inc., DSPIC30F4012 Datasheet - Page 226
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DSPIC30F4012
Manufacturer Part Number
DSPIC30F4012
Description
Dspic30f4011/4012 Enhanced Flash 16-bit Digital Signal Controller
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC30F4012.pdf
(236 pages)
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dsPIC30F4011/4012
Data EEPROM Memory ...................................................... 51
DC Characteristics ............................................................ 171
DC Temperature and Voltage Specifications .................... 172
Dead-Time Generators ....................................................... 96
Development Support ....................................................... 167
Device Configuration
Device Configuration Registers......................................... 156
Divide Support..................................................................... 16
DSP Engine......................................................................... 16
dsPIC30F4011 Port Register Map ...................................... 59
dsPIC30F4012 Port Register Map ...................................... 60
Dual Output Compare Match Mode .................................... 82
E
Edge-Aligned PWM............................................................. 95
Electrical Characteristics................................................... 171
Equations
Errata .................................................................................... 6
External Interrupt Requests ................................................ 43
F
Fast Context Saving............................................................ 43
Flash Program Memory....................................................... 45
I
I/O Ports
I
DS70135E-page 224
2
C Module
Erasing ........................................................................ 52
Erasing, Block ............................................................. 52
Erasing, Word ............................................................. 52
Protection Against Spurious Write .............................. 55
Reading....................................................................... 51
Write Verify ................................................................. 55
Writing ......................................................................... 53
Writing, Block .............................................................. 54
Writing, Word .............................................................. 53
BOR .......................................................................... 178
I/O Pin Input Specifications ....................................... 176
I/O Pin Output Specifications .................................... 177
Idle Current (I
Operating Current (I
Power-Down Current (I
Program and EEPROM............................................. 178
Ranges........................................................................ 97
Register Map............................................................. 158
FBORPOR ................................................................ 156
FGS........................................................................... 156
FOSC ........................................................................ 156
FWDT........................................................................ 156
Multiplier...................................................................... 18
Continuous Output Pulse Mode .................................. 82
Single Output Pulse Mode .......................................... 82
A/D Conversion Clock ............................................... 136
Baud Rate ................................................................. 119
I2CBRG Value .......................................................... 112
PWM Period ................................................................ 94
PWM Period (Center-Aligned Mode) .......................... 94
PWM Resolution ......................................................... 94
Time Quantum for Clock Generation ........................ 129
In-Circuit Serial Programming (ICSP) ......................... 45
Run-Time Self-Programming (RTSP) ......................... 45
Table Instruction Operation Summary ........................ 45
Parallel I/O (PIO)......................................................... 57
10-bit Slave Mode Operation .................................... 109
Reception.......................................................... 110
Transmission..................................................... 110
IDLE
) .................................................... 174
DD
)............................................. 173
PD
) ........................................ 175
In-Circuit Serial Programming (ICSP)............................... 145
Independent PWM Output .................................................. 98
Initialization Condition for RCON Register, Case 2 .......... 154
Initialization Condition for RCON Register, Case 1 .......... 154
Input Capture Module ......................................................... 77
Input Change Notification Module....................................... 61
Input Diagrams
Instruction Addressing Modes ............................................ 33
Instruction Set Overview................................................... 162
Instruction Set Summary .................................................. 159
Internal Clock Timing Examples ....................................... 182
Internet Address ............................................................... 228
Interrupt Controller
Interrupt Priority .................................................................. 40
Interrupt Sequence ............................................................. 43
7-bit Slave Mode Operation ...................................... 109
Addresses................................................................. 109
Automatic Clock Stretch ........................................... 110
General Call Address Support .................................. 111
Interrupts .................................................................. 111
IPMI Support............................................................. 111
Master Operation ...................................................... 111
Master Support ......................................................... 111
Operating Function Description ................................ 107
Operation During CPU Sleep and
Pin Configuration ...................................................... 107
Programmer’s Model ................................................ 107
Register Map ............................................................ 113
Registers .................................................................. 107
Slope Control ............................................................ 111
Software Controlled Clock Stretching
Various Modes.......................................................... 107
In CPU Idle Mode ....................................................... 79
In CPU Sleep Mode .................................................... 78
Interrupts .................................................................... 79
Register Map .............................................................. 80
Simple Capture Event Mode....................................... 78
Register Map (bits 7-0) ............................................... 61
QEA/QEB Input ........................................................ 194
File Register Instructions ............................................ 33
Fundamental Modes Supported ................................. 33
MAC Instructions ........................................................ 34
MCU Instructions ........................................................ 33
Move and Accumulator Instructions............................ 34
Other Instructions ....................................................... 34
Register Map .............................................................. 44
Interrupt Stack Frame ................................................. 43
Reception ......................................................... 109
Transmission .................................................... 109
During 10-bit Addressing (STREN = 1) ............ 110
During 7-bit Addressing (STREN = 1) .............. 110
Reception ......................................................... 110
Transmission .................................................... 110
Baud Rate Generator (BRG) ............................ 112
Clock Operation................................................ 112
Multi-Master Communication, Bus
Reception ......................................................... 112
Transmission .................................................... 111
Idle Modes ........................................................ 112
(STREN = 1) ..................................................... 110
Collision and Arbitration............................ 112
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