DSPIC30F4012 Microchip Technology Inc., DSPIC30F4012 Datasheet - Page 35

• Manufacturer Part Number: DSPIC30F4012
• Description: Dspic30f4011/4012 Enhanced Flash 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

4.0
The dsPIC DSC core contains two independent
address generator units: the X AGU and Y AGU. The Y
AGU supports word-sized data reads for the DSP MAC
class of instructions only. The dsPIC Digital Signal
Controller
addressing:
• Linear Addressing
• Modulo (Circular) Addressing
• Bit-Reversed Addressing
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
Addressing is only applicable to data space addresses.
4.1
The addressing modes in Table 4-1 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
TABLE 4-1:
© 2007 Microchip Technology Inc.
File Register Direct
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
ADDRESS GENERATOR UNITS
Instruction Addressing Modes
Addressing Mode
AGUs support three types of data
FUNDAMENTAL ADDRESSING MODES SUPPORTED
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the EA.
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
The sum of Wn and a literal forms the EA.
4.1.1
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first
8192 bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register, or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space during file register
operation.
4.1.2
The three-operand MCU instructions are of the form:
where Operand 1 is always a working register (i.e., the
addressing mode can only be Register Direct), which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory or a 5-bit literal. The result
location can either be a W register or an address
location.
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
Note:
dsPIC30F4011/4012
Operand 3 = Operand 1 <function> Operand 2
Description
The
FILE REGISTER INSTRUCTIONS
MCU INSTRUCTIONS
Not all instructions support all the address-
ing
instructions may support different subsets
of these addressing modes.
following
modes
given
addressing
above.
DS70135E-page 33
modes
Individual
are