DSPIC30F6012A Microchip Technology Inc., DSPIC30F6012A Datasheet - Page 234
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
DSPIC30F6012A
Manufacturer Part Number
DSPIC30F6012A
Description
Dspic30f6011a/6012a/6013a/6014a High-performance Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC30F6012A.pdf
(238 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6012A-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
DSPIC30F6012A-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
DSPIC30F6012A-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
DSPIC30F6012A-30I/PF
Manufacturer:
Holtek
Quantity:
175
Company:
Part Number:
DSPIC30F6012A-30I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F6012A-30I/PF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
DSPIC30F6012A-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F6012A-30I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
DSPIC30F6012AT-20E/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
DSPIC30F6012AT-30E/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
DSPIC30F6012AT-30I/PF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F6011A/6012A/6013A/6014A
Trap Vectors........................................................................ 48
Traps ................................................................................... 47
U
UART Module
UART Operation
Unit ID Locations............................................................... 143
Universal Asynchronous Receiver Transmitter. See UART.
W
Wake-up from Sleep ......................................................... 143
Wake-up from Sleep and Idle.............................................. 49
Watchdog Timer (WDT) ............................................ 143, 158
WWW Address.................................................................. 233
WWW, On-Line Support........................................................ 7
DS70143C-page 232
Hard and Soft .............................................................. 48
Sources ....................................................................... 47
Address Detect Mode ............................................... 107
Auto Baud Support.................................................... 108
Baud Rate Generator ................................................ 107
Enabling and Setting Up ........................................... 105
Framing Error (FERR)............................................... 107
Idle Status ................................................................. 107
Loopback Mode ........................................................ 107
Operation During CPU Sleep and Idle Modes .......... 108
Overview ................................................................... 103
Parity Error (PERR) .................................................. 107
Receive Break........................................................... 107
Receive Buffer (UxRXB) ........................................... 106
Receive Buffer Overrun Error (OERR Bit) ................ 106
Receive Interrupt....................................................... 106
Receiving Data.......................................................... 106
Receiving in 8-bit or 9-bit Data Mode........................ 106
Reception Error Handling.......................................... 106
Transmit Break.......................................................... 106
Transmit Buffer (UxTXB)........................................... 105
Transmit Interrupt...................................................... 106
Transmitting Data...................................................... 105
Transmitting in 8-bit Data Mode ................................ 105
Transmitting in 9-bit Data Mode ................................ 105
UART1 Register Map ................................................ 109
UART2 Register Map ................................................ 109
Idle Mode .................................................................. 108
Sleep Mode ............................................................... 108
Enabling and Disabling ............................................. 158
Operation .................................................................. 158
Timing Characteristics .............................................. 189
Timing Requirements ................................................ 190
Address Error Trap ............................................. 47
Math Error Trap................................................... 47
Oscillator Fail Trap.............................................. 48
Stack Error Trap.................................................. 48
Preliminary
© 2006 Microchip Technology Inc.