DSPIC30F6015 Microchip Technology Inc., DSPIC30F6015 Datasheet - Page 122

• Manufacturer Part Number: DSPIC30F6015
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC30F6010A/6015
18.9
To allow the system to determine baud rates of
received characters, the input can be optionally linked
to a selected capture input. To enable this mode, the
user must program the input capture module to detect
the falling and rising edges of the Start bit.
18.10 UART Operation During CPU
18.10.1
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic ‘0’. If
entry into Sleep mode occurs while a transmission is
in progress, then the transmission is aborted. The
UxTX pin is driven to logic ‘1’. Similarly, if entry into
Sleep mode occurs while a reception is in progress,
then the reception is aborted. The UxSTA, UxMODE,
Transmit and Receive registers and buffers, and the
UxBRG register are not affected by Sleep mode.
If the Wake bit (UxMODE<7>) is set before the device
enters Sleep mode, then a falling edge on the UxRX
pin will generate a receive interrupt. The Receive
Interrupt Select Mode bit (URXISEL) has no effect for
this function. If the receive interrupt is enabled, then
this will wake-up the device from Sleep. The UARTEN
bit must be set in order to generate a wake-up
interrupt.
DS70150C-page 120
Auto-Baud Support
Sleep and Idle Modes
UART OPERATION DURING CPU
SLEEP MODE
18.10.2
For the UART, the USIDL bit selects if the module will
stop operation when the device enters Idle mode, or
whether the module will continue on Idle. If USIDL = 0,
the module will continue operation during Idle mode. If
USIDL = 1, the module will stop on Idle.
UART OPERATION DURING CPU
IDLE MODE
© 2007 Microchip Technology Inc.