DSPIC30F6015 Microchip Technology Inc., DSPIC30F6015 Datasheet - Page 155

• Manufacturer Part Number: DSPIC30F6015
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

21.2.8
A write to the OSCCON register is intentionally made
difficult because it controls clock switching and clock
scaling.
To write to the OSCCON low byte, the following code
sequence must be executed without any other
instructions in between:
Byte write is allowed for one instruction cycle. Write the
desired value or use bit manipulation instruction.
To write to the OSCCON high byte, the following
instructions must be executed without any other
instructions in between:
Byte write is allowed for one instruction cycle. Write the
desired value or use bit manipulation instruction.
FIGURE 21-2:
© 2007 Microchip Technology Inc.
Byte Write “0x46” to OSCCON low
Byte Write “0x57” to OSCCON low
Byte Write “0x78” to OSCCON high
Byte Write “0x9A” to OSCCON high
MCLR
V
Illegal Opcode/
Uninitialized W Register
DD
Instruction
RESET
PROTECTION AGAINST
ACCIDENTAL WRITES TO OSCCON
Trap Conflict
Brown-out
V
Sleep or Idle
Module
Detect
DD
WDT
Reset
RESET SYSTEM BLOCK DIAGRAM
Rise
BOREN
Glitch Filter
Digital
POR
BOR
dsPIC30F6010A/6015
21.3
The dsPIC30F differentiates between various kinds of
Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Different registers are affected in different ways by
various Reset conditions. Most registers are not
affected by a WDT wake-up, since this is viewed as the
resumption of normal operation. Status bits from the
RCON register are set or cleared differently in different
Reset situations, as indicated in Table 21-5. These bits
are used in software to determine the nature of the
Reset.
A block diagram of the on-chip Reset circuit is shown in
Figure 21-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Reset caused by trap lockup (TRAPR)
Reset caused by illegal opcode, or by using an
uninitialized W register as an Address Pointer
(IOPUWR)
Reset
S
R
Q
DS70150C-page 153
SYSRST