DSPIC30F6015 Microchip Technology Inc., DSPIC30F6015 Datasheet - Page 140

• Manufacturer Part Number: DSPIC30F6015
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC30F6010A/6015
20.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the
conversion trigger.
The SSRC bits provide for up to 5 alternate sources of
conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the con-
version trigger is under A/D clock control. The SAMC
bits select the number of A/D clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least 1 clock cycle.
Other trigger sources can come from timer modules,
motor control PWM module, or external interrupts.
20.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing. The ADCBUF will not be updated with the partially
completed A/D conversion sample. That is, the
ADCBUF will continue to contain the value of the last
completed conversion (or the last value written to the
ADCBUF register).
If the clearing of the ADON bit coincides with an
auto-start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 T
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the
next channel converted. If simultaneous sampling is
specified, the A/D will continue with the next
multichannel group conversion sequence.
DS70150C-page 138
Note:
Programming the Start of
Conversion Trigger
Aborting a Conversion
To operate the A/D at the maximum speci-
fied conversion speed, the Auto-Convert
Trigger
(SSRC = 111) and the Auto-Sample Time
bits
(SAMC = 00001). This configuration will
give a total conversion period (sample +
convert) of 13 T
The use of any other conversion trigger
will result in additional T
synchronize the external event to the A/D.
should
option
AD
be
.
should
set
AD
be
to
cycles to
AD
selected
1
wait is
T
AD
20.6
The A/D conversion requires 12 T
A/D conversion clock is software selected using a six-
bit counter. There are 64 possible options for T
EQUATION 20-1:
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(T
of 83.33 nsec (for V
"Electrical Characteristics" for minimum T
other operating conditions.
Example 20-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 20-1:
AD
) must be selected to ensure a minimum T
Therefore,
Set ADCS<5:0> = 9
Selecting the A/D Conversion
Clock
T
ADCS<5:0> = 2
Actual T
AD
= T
ADCS<5:0> = 2
CY
AD
T
T
DD
* (0.5 * (ADCS<5:0> + 1))
AD
CY
= 2 •
= 4.09
=
=
= 99 nsec
= 5V). Refer to the Section 24.0
A/D CONVERSION CLOCK
CALCULATION
A/D CONVERSION CLOCK
= 33 nsec (30 MIPS)
= 84 nsec
© 2007 Microchip Technology Inc.
T
33 nsec
T
T
CY
2
AD
CY
84 nsec
2
33 nsec
(ADCS<5:0> + 1)
T
T
– 1
AD
CY
AD
(9 + 1)
. The source of the
– 1
– 1
AD
AD
AD
under
.
time