FIDO1100PQF208IR1 Innovasic Semiconductor Inc., FIDO1100PQF208IR1 Datasheet - Page 59

• Manufacturer Part Number: FIDO1100PQF208IR1
• Description: 32-bit Real-time Communications Controller
• Manufacturer: Innovasic Semiconductor Inc.

Flexible Input Deterministic Output (fido ® )
32-Bit Real-Time Communications Controller
9.1.1 External Bus Timing for a 32-Bit Transfer (without RDY_N)
This timing is programmable via the External Bus Chip Select Timing Register (see Figure 20).
Minimum Pulse Width—The minimum length of time between the leading and trailing
edges of a pulse (see Figure 19).
THLD—Specifies the time between when the CSn_N and BEn_N signals go inactive (hi)
and the address is removed, 0–7 clocks.
TCS—Specifies the time between when the address bus is driven and the CSn_N and
BEn_N signals go active (low), 0–3 clocks.
TOE—Specifies the time between when the CSn_N and BEn_N signals go active (low)
and the OE signal goes active (low), 0–3 clocks.
TWEF—Specifies the time between when the CSn_N and BEn_N signals go active (low)
and the WE_N signal goes active (low), 0–3 clocks.
TWER—Specifies the time between when the WE_N signal goes inactive (hi) and the
CSn_N and BEn_N signals go inactive (hi), 0–3 clocks.
All timing is relative to the rising edge of the clock.
The chip-select and byte-enable signals (CSn_N and BEn_N) go active (low) 0–3 clocks
(TCS) after the address bus is driven.
The chip-select, output-enable, and byte-enable signals (CSn_N, BEn_N, and OE_N) go
inactive (hi) 0–7 clocks (THLD) before the address is removed (on the last cycle).
Timings are based on a 66-MHz clock yielding 15-ns cycles.
MPW_H = 7ns.
MPW_L = 7ns.
®
Figure 19. Minimum Pulse Width
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IA211080807-06
November 20, 2009
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