ADN2817 Analog Devices, Inc., ADN2817 Datasheet
ADN2817
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ADN2817 Summary of contents
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... The ADN2817/ADN2818 have many optional features available through an I the data rate onto which the ADN2817 or ADN2818 is locked, or the user can set the device to lock only to one particular data rate if provisioning of data rates is required. The ADN2817/ADN2818 are available in compact 5 mm × 5 mm, 32-lead, lead frame chip scale packages ...
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... Frequency Acquisition ............................................................... 19 Lock Detector Operation .......................................................... 19 Harmonic Detector .................................................................... 20 Limiting Amplifier (ADN2817 Only) ..................................... 20 Slice Level Adjust (ADN2817 Only) ........................................ 20 Loss of Signal (LOS) Detector (ADN2817 Only).................. 20 Squelch Mode ............................................................................. 20 Interface ................................................................................ 21 Reference Clock (Optional) ...................................................... 21 Additional Features Available via the I ...
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... DC-coupled (see Figure 39, Figure 40, and Figure 41 − 1 PRBS, ac-coupled 1 , BER = 1 × 10 −10 ADN2817 ADN2818 @ 2.5 GHz Differential ADN2817 only SLICEP − SLICEN = ±0.5 V SLICEP − SLICEN DC level @ SLICEP or SLICEN ADN2817 only Ω Thresh R = 100 kΩ Thresh Ω Thresh R = 100 kΩ Thresh Ω ...
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... ADN2818 OPERATING TEMPERATURE RANGE 1 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity. 2 When ac-coupled, the LOS assert and deassert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the ADN2817 input stage. JITTER SPECIFICATIONS ...
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... BUF Optional lock to REFCLK mode @ REFCLKP or REFCLKN 2 2 0.4 V − Rev Page ADN2817/ADN2818 Typ Max Unit 350 600 mV 700 1200 mV VCC V VCC − 0.35 VCC − 0 112 ps 80 123 ps 200 250 ps 200 250 ...
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... ADN2817/ADN2818 Parameter LVTTL DC OUTPUT CHARACTERISTICS Output Voltage High Low Timing Characteristics CLKOUTP DATAOUTP/ DATAOUTN OUTP V OUTN OUTP – OUTN 0V CLKOUTP/ CLKOUTN DATAOUTP/ CLKOUTN Conditions −2 +2 Figure 2. Default Mode Output Timing CML DIFF Figure 3. Single-Ended vs. Differential Output Specifications ...
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... THERMAL CHARACTERISTICS = F Thermal Resistance 32-lead LFCSP, 4-layer board with exposed paddle soldered to VEE: θ = 28°C/W. JA Rating ESD CAUTION 4.2 V VEE − 0.4 V VCC + 0.4 V 125°C −65°C to +150°C 300°C Rev Page ADN2817/ADN2818 ...
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... SQUELCH DI 28 DATAOUTN DO 29 DATAOUTP DO 30 VEE TEST1 1 VCC 2 VREF 3 ADN2817/ADN2818 NIN 4 TOP VIEW PIN 5 (Not to Scale) SLICEP 6 SLICEN 7 VEE NOTES 1. EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE CONNECTED TO VEE. Figure 5. Pin Configuration ...
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... Pin No. Mnemonic Type 31 VCC P 32 TEST2 Exposed Pad Pad power analog input analog output digital input digital output. 1 Description Phase Detector, Phase Shifter Power. Connect to VCC Connect to GND. Note that the exposed paddle must be connected to VEE. Rev Page ADN2817/ADN2818 ...
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... JITTER FREQUENCY (Hz) Figure 8. Jitter Transfer, OC-3 10k 100k 1M SONET 100k 1M SONET 1M 10M Rev Page 50ps/DIV Figure 9. ADN2817/ADN2818 Output Eye, OC-48 100 10 1 ADN2817 EQUIPMENT LIMIT SONET GR-253 CORE 004 0.1 10 100 1k 10k JITTER FREQUENCY (Hz) Figure 10. Jitter Tolerance, OC-1 100 10 1 ADN2817 ...
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... ADN2817 –10 –15 –20 10k 100k 1M 10M JITTER FREQUENCY (Hz) Figure 13. Jitter Transfer, OC-48 0.70 0.65 0.60 0.55 0.50 0.45 0.40 CLKOUTP ADN2817 BOOST 0.35 CLKOUTN ADN2817 BOOST CLKOUTP ADN2817 NO BOOST CLKOUTN ADN2817 NO BOOST 0.30 100M 600M 1.1G 1.6G 2.1G DATA RATE (Hz) Figure 14. Output Swing vs. Data Rate 1000 100 10 1 0.1 10M 10 1000 100 10 1 0.1 100M 10 10e– ...
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... ADN2817/ADN2818 INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION S SLAVE ADDR, LSB = 0 (WR) A(S) S SLAVE ADDR, LSB = 0 (WR START BIT A(S) = ACKNOWLEDGE BY SLAVE START BIT SLAVE ADDRESS SDA A6 A5 SCK S SLADDR[4: SDA t SCK S SLAVE ADDRESS [6: MSB = 1 SET BY PIN 19 Figure 18. Slave Address Configuration ...
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... HI_CODE[8:1] LO_CODE[8: Static LOL LOL Status waiting for next 0 = locked LOL 1 = static LOL until 1 = reset acquiring Rev Page ADN2817/ADN2818 LOL Status Data Rate 0 Measurement Complete Measure Data Rate Reset 0 0 MISC[2] 0 Config LOS Squelch Mode Initiate ...
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... ADN2817/ADN2818 Table 8. Control Register, CTRLA f Range REF D7 D6 Set to 0 Set MHz to 25 MHz Set to 0 Set MHz to 50 MHz Set to 1 Set MHz to 100 MHz Set to 1 Set to 1 100 MHz to 200 MHz Table 9. Control Register, CTRLB ...
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... LOS output, Pin 22. When the inputs are dc-coupled, the LOS assert time of the ADN2817 is 450 ns typically and the deassert time is 500 ns typically. In practice, the time constant produced by the ac coupling at the quantizer input and the 50 Ω on-chip input termination determine the LOS response time ...
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... ADN2817/ADN2818 JITTER SPECIFICATIONS The ADN2817/ADN2818 CDR is designed to achieve the best bit-error-rate (BER) performance and exceeds the jitter transfer, generation, and tolerance specifications proposed for SONET/SDH equipment defined in the Telcordia® Technologies specification. Jitter is the dynamic displacement of digital signal edges from their long-term average positions, measured in unit intervals (UI), where bit period ...
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... Figure 28. ADN2817/ADN2818 PLL/DLL Architecture o n psh FREQUENCY (kHz) Figure 29. ADN2817/ADN2818 Jitter Response vs. Conventional PLL The delay- and phase-locked loops contribute to overall jitter accommodation. At low frequencies of input jitter on the data signal, the integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error. In this case, the VCO is frequency modulated and jitter is tracked ordinary phase-locked loop ...
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... ADN2817/ADN2818 At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one extreme of its tuning range or the other. The size of the VCO tuning range, therefore, has only a small effect on the jitter accommodation ...
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... MISC[4] bit and has the function- ality described in the previous paragraph. The CTRLB[7] bit defaults this mode, the LOL pin operates in the normal operating mode, that is asserted only when the ADN2817/ ADN2818 are in acquisition mode and deasserts when the ADN2817/ADN2818 reacquire lock. ...
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... The threshold is set with a single external resistor from Pin 9, THRADJ, to VEE. The LOS comparator trip point vs. resistor value is illustrated in Figure 6. If the input level to the ADN2817 drops below the programmed LOS threshold, the output of the LOS detector, LOS Pin 22, is asserted to a Logic 1. The LOS detector response time is 450 ns by design, but is dominated by the RC time constant in ac-coupled applications ...
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... The ADN2817/ADN2818 act as standard slave devices on the bus. The data on the SDA pin is eight bits long supporting the 7-bit addresses plus the R/ W bit. The ADN2817/ADN2818 have eight subaddresses to enable the user-accessible internal registers (see ...
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... Data Rate/2 = REFCLK/2 The user must know exactly what the data rate is, and provide a reference clock that is a function of this rate. The ADN2817/ ADN2818 can still be used as continuous rate devices in this configuration if a reference clock with a variable frequency is provided (see Application Note AN-632). ...
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... HI_CODE and the code value for the low limit data rate into LO_CODE to set the appropriate range. For example, if the user wants to limit the acquisition range of the ADN2817/ADN2818 to lock between 1 Gbps and 1.25 Gbps Plugging this value the following steps must be taken: 1 ...
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... CDR Bypass Mode The CDR on the ADN2817/ADN2818 can be bypassed by setting Bit CTRLD[ this mode, the ADN2817/ADN2818 feed the input directly through the input amplifiers to the output buffer, completely bypassing the CDR ...
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... Use μF electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they should be placed between the IC power supply (VCC and VEE), as close as possible to the ADN2817/ADN2818 VCC pins. VCC + 10µF 0.1µ ...
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... PDJ ps p-p 3kΩ <0.01 UI p-p typical the rise time, which is equal to 0.22/BW, r where BW ~ 0.7 (bit rate). Note that this expression for t The output rise time for the ADN2817/ADN2818 is ~100 ps regardless of data rate. Rev Page –t/τ (1 − therefore, τ = 12t p-p Τ − ...
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... HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER DOES NOT RECOGNIZE THIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2817. THE QUANTIZER RECOGNIZES BOTH HIGH AND LOW STATES AT THIS POINT. ...
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... ADN2817/ADN2818 COARSE DATA RATE READBACK LOOK-UP TABLE Code is the 9-bit value read back from COARSE_RD[8:0]. Table 16. Coarse Data Rate Readback Look-Up Table Code FMID Code 0 5.3205E 5.3202E 5.4294E 5.5473E 5.6735E 5.8086E 5.9533E 6.1087E 6.2771E+6 ...
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... Rev Page ADN2817/ADN2818 Code FMID 265 1.6567E+9 266 1.7076E+9 267 1.7634E+9 268 1.8245E+9 269 1.8916E+9 270 1.9658E+9 271 2.0477E+9 272 1.9524E+9 273 1 ...
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... ADN2817/ADN2818 HI_CODE AND LO_CODE LOOK-UP TABLE Code is the 9-bit value to be written into HI_CODE[8:0] and LO_CODE[8:0]. Use the high limit code for HI_CODE and the low limit code for LO_CODE. Table 17. Code Low Limit 0 5.7633E+6 1 5.7631E+6 2 5.8777E+6 3 6.0011E+6 4 6.1328E+6 5 6.2738E+6 6 6.4245E ...
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... Rev Page ADN2817/ADN2818 Low Limit High Limit 144.5697E+6 122.5977E+6 148.2068E+6 125.9286E+6 152.1160E+6 129.5324E+6 156.3320E+6 133.4459E+6 161.1721E+6 137.9770E+6 166.1317E+6 142.6637E+6 171.5227E+6 147.8032E+6 177.3906E+6 153.4634E+6 183 ...
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... ADN2817/ADN2818 Code Low Limit 202 458.5027E+6 203 472.7012E+6 204 488.2673E+6 205 505.2599E+6 206 523.8745E+6 207 544.3897E+6 208 529.3112E+6 209 529.2874E+6 210 540.2475E+6 211 552.0658E+6 212 564.7314E+6 213 578.2786E+6 214 592.8272E+6 215 608.4642E+6 216 625.3279E+6 217 644.6885E+6 218 664.5266E+6 219 686.0907E+6 220 709 ...
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... Dimensions shown in millimeters Package Description 32-Lead LFCSP 32-Lead LFCSP, Tape and Reel 32-Lead LFCSP, Tape and Reel 32-Lead LFCSP 32-Lead LFCSP, Tape and Reel 32-Lead LFCSP, Tape and Reel Evaluation Board Evaluation Board Rev Page ADN2817/ADN2818 0.60 MAX PIN 1 INDICATOR 3.25 EXPOSED PAD 3.10 SQ (BOTTOM VIEW) 2 ...
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... ADN2817/ADN2818 NOTES Rev Page ...
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... NOTES Rev Page ADN2817/ADN2818 ...
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... ADN2817/ADN2818 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...