ADN2817 Analog Devices, Inc., ADN2817 Datasheet - Page 25

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ADN2817

Manufacturer Part Number
ADN2817
Description
Continuous Rate 10 Mbps To 2.7gb/s Clock And Data Recovery Ics
Manufacturer
Analog Devices, Inc.
Datasheet

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APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
For best practice, the use of one low impedance ground plane is
recommended. To reduce series inductance, solder the VEE pins
directly to the ground plane. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 23, which is the ground return for
the output buffers. Connect the exposed pad to the GND plane
using plugged vias so that solder does not leak through the vias
during reflow.
Use of a 10 μF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they
should be placed between the IC power supply (VCC and VEE),
as close as possible to the ADN2817/ADN2818 VCC pins.
VCC
VCC
TIA
0.1µF
+
50Ω
50Ω
10µF
0.1µF
1nF
C
IN
Figure 35. Typical ADN2817/ADN2818 Applications Circuit
0.1µF
SLICEN
SLICEP
TEST1
VREF
VCC
VEE
NIN
PIN
10kΩ
1nF
VCC
1
2
3
4
5
6
7
8
10kΩ
R
Rev. 0 | Page 25 of 36
TH
0.1µF
32
9
4 × 100Ω
31
10
PLANE WITH VIAS.
1nF
30
TIED OFF TO VEE
11
(Not to Scale)
ADN2817/
EXPOSED PAD
ADN2818
TOP VIEW
29
12
If connections to the supply and ground are made through
vias, the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/DATAOUTN
output buffers. See the schematic in Figure 35 for recommended
connections.
By using adjacent power supply and GND planes, excellent high
frequency decoupling can be realized by using close spacing
between the planes. This capacitance is given by
where:
ε
A is the area of the overlap of power and GND planes (cm
d is the separation between planes (mm).
For FR-4, ε
r
28
13
is the dielectric constant of the PCB material.
VCC
C
27
14
0.47µF +20%
>300MΩ
INSULATION RESISTANCE
PLANE
26
15
r
= 0.88ε
25
16
= 4.4 and 0.25 mm spacing, C ~15 pF/cm
24
23
22
21
20
19
18
17
50Ω TRANSMISSION
r
VCC
VEE
LOS
SDA
SCK
SADDR5
VCC
VEE
A/d (pF)
µC
LINES
I
µC
2
C CONTROLLER
1nF
1nF
ADN2817/ADN2818
0.1µF
DATAOUTP
DATAOUTN
CLKOUTP
CLKOUTN
VCC
0.1µF
VCC
2
.
2
).

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