ADN2817 Analog Devices, Inc., ADN2817 Datasheet - Page 22

• Manufacturer Part Number: ADN2817
• Description: Continuous Rate 10 Mbps To 2.7gb/s Clock And Data Recovery Ics
• Manufacturer: Analog Devices, Inc.

ADN2817/ADN2818
The two uses of the reference clock are mutually exclusive. The
reference clock can be used either as an acquisition aid for the
ADN2817/ADN2818 to lock onto data, or to measure the fre-
quency of the incoming data to within 0.01%. (There is the
capability to measure the data rate to approximately ±10%
without the use of a reference clock.) The modes are mutually
exclusive, because, in the first use, the user knows exactly what
the data rate is and wants to force the part to lock onto only that
data rate; in the second use, the user does not know what the
data rate is and wants to measure it.
Lock to reference mode is enabled by writing 1 to I
Bit CTRLA[0]. Fine data rate readback mode is enabled by
writing 1 to I
of these bits at the same time causes an indeterminate state
and is not supported.
Using the Reference Clock to Lock onto Data
Writing CTRLA[0] = 1 puts the ADN2817/ADN2818 into lock
to REFCLK (LTR) mode. In this mode, the ADN2817/ADN2818
lock onto a frequency derived from the reference clock according
to the following equation:
The user must know exactly what the data rate is, and provide
a reference clock that is a function of this rate. The ADN2817/
ADN2818 can still be used as continuous rate devices in this
configuration if a reference clock with a variable frequency is
provided (see Application Note AN-632).
The reference clock can be anywhere between 10 MHz and
200 MHz. By default, the ADN2817/ADN2818 expect a
reference clock of between 10 MHz and 25 MHz. If it is between
25 MHz and 50 MHz, 50 MHz and 100 MHz, or 100 MHz and
200 MHz, the user needs to configure the ADN2817/ADN2818
to use the correct reference frequency range by setting two bits
of the CTRLA register, CTRLA[7:6].
Table 14. CTRLA[7:6] (f
Ratio) Settings
CTRLA[7:6]
00
01
10
11
Data Rate/2
2
C Register Bit CTRLA[1]. Writing a 1 to both
VCC
Range (MHz)
10 to 25
25 to 50
50 to 100
100 to 200
REFCLKN
CTRLA[5:2]
REFCLKP
Figure 34. No REFCLK Configuration
10
11
= REFCLK/2
REF
100kΩ
ADN2817/ADN2818
Range)with CTRLA[5:2] (f
100kΩ
BUFFER
CTRLA[7:6]
CTRLA[5:2]
0000
0001
n
1000
VCC/2
2
C Register
REF
Ratio
1
2
2
256
n
Rev. 0 | Page 22 of 36
The user can specify a fixed integer multiple of the reference
clock to lock onto using CTRLA[5:2], where CTRLA should be
set to the data rate/DIV_FREF and DIV_FREF represents the
divided-down reference referred to the 10 MHz to 25 MHz band.
For example, if the reference clock frequency is 38.88 MHz and
the input data rate is 622.08 Mbps, then CTRLA[7:6] is set to
[01] to give a divided-down reference clock of 19.44 MHz.
CTRLA[5:2] is set to [0101], that is, 5, because
When the CTRLA[7:2] value is correct and CTRLA[0] has been
written to a Logic 1, it is recommended that a 1 to 0 transition
be written to CTRLB[5] to initiate a new frequency acquisition
with respect to the reference clock.
In this mode, if the ADN2817/ADN2818 lose lock for any
reason, they relock onto the reference clock and continue to
output a stable clock.
Though the ADN2817/ADN2818 operate in LTR mode, if
the user ever changes the reference frequency, the f
(CTRLA[7:6]), or the f
followed by writing a 1 to 0 transition into the CTRLB[5] bit
to initiate a new frequency acquisition.
A frequency acquisition can also be initiated in LTR mode by
writing a 0 to 1 transition into CTRLA[0], however, it is rec-
ommended that a frequency acquisition is initiated by writing
a 1 to 0 transition into CTRLB[5] as explained previously.
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2817/ADN2818 compare the
frequency of the incoming data to the incoming reference clock
and return a ratio of the two frequencies to 0.01% (100 ppm).
The accuracy error of the reference clock is added to the
accuracy of the ADN2817/ADN2818 data rate measurement.
For example, if a 100 ppm accuracy reference clock is used, the
total accuracy of the measurement is within 200 ppm.
The reference clock can range from 10 MHz to 200 MHz. The
ADN2817/ADN2818 expects a reference clock between
10 MHz and 25 MHz by default. If it is between 25 MHz and
50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz,
the user needs to configure the ADN2817/ADN2818 to use
the correct reference frequency range by setting two bits of
the CTRLA register, CTRLA[7:6]. Using the reference clock to
determine the frequency of the incoming data does not affect
the manner in which the part locks onto data. In this mode, the
reference clock is used only to determine the frequency of the
data. For this reason, the user does not need to know the data
rate to use the reference clock in this manner.
Prior to reading back the data rate using the reference clock, the
CTRLA[7:6] bits must be set to the appropriate frequency range
with respect to the reference clock being used. A fine data rate
readback is then executed as follows:
622.08 Mbps/19.44 MHz = 2
REF
ratio (CTRLA[5:2]), this must be
5
REF
range