ADN2817 Analog Devices, Inc., ADN2817 Datasheet - Page 23

• Manufacturer Part Number: ADN2817
• Description: Continuous Rate 10 Mbps To 2.7gb/s Clock And Data Recovery Ics
• Manufacturer: Analog Devices, Inc.

Step 1. Write a 1 to CTRLA[1]. This enables the fine data rate
measurement capability of the ADN2817/ADN2818. This bit is
level sensitive and does not need to be reset to perform
subsequent frequency measurements.
Step 2. Reset MISC[2] by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement.
Step 3. Readback MISC[2]. If it is 0, the measurement is not
complete. If it is 1, the measurement is complete and the data
rate can be read back on FREQ[22:0]. The time for a data rate
measurement is typically 80 ms.
Step 4. Read back the data rate from the FREQ2[6:0],
FREQ1[7:0], and FREQ0[7:0] registers.
Use the following equation to determine the data rate:
where:
FREQ[22:0] is the reading from FREQ2[6:0] (most significant
byte), FREQ1[7:0], and FREQ0[7:0] (least significant byte). See
Table 15.
f
f
SEL_RATE is the setting from CTRLA[7:6].
Table 15.
D22
For example, if the reference clock frequency is 32 MHz, it falls
within the 25 MHz to 50 MHz range; therefore, the CTRLA[7:6]
setting is [01] resulting in SEL_RATE = 1. For this example, the
input data rate is 2.488 Gbps (OC-48). After following Step 1
through Step 4, the value that is read back on FREQ[22:0] =
0x26E010, which is equal to 2.5477 × 10
into the equation yields
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The
measurement process is reset by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement. Follow
Step 2 through Step 4 to read back the new data rate.
Note that a data rate readback is valid only if LOL is low. If LOL
is high, the data rate readback is invalid.
ADDITIONAL FEATURES AVAILABLE VIA THE I
INTERFACE
Coarse Data Rate Readback
The data rate can be read back over the I
approximately ±10% without needing an external reference
clock. A 9-bit register, COARSE_RD[8:0], can be read back
when LOL is deasserted. The 8 MSBs of this register are the
contents of the RATE[7:0] register. The LSB of the COARSE_RD
register is Bit MISC[0].
DATARATE
REFCLK
(
f
. 2
FREQ2[6:0]
is the REFCLK frequency (MHz).
DATARATE
D21...D17
5477
is the data rate (Mbps).
6 e
×
=
32
(
FREQ
D16
6 e
)
2 /
(
[
D15
22
(
14
0 ..
+
) 1
FREQ1[7:0]
]
)
×
D14...D9
=
f
. 2
REFCLK
488
Gbps
)
6
2
2 /
. Plugging this value
D8
C interface to
(
14
+
SEL
D7
_
RATE
FREQ0[7:0]
D6...D1
)
2
C
Rev. 0 | Page 23 of 36
D0
Table 16 is a look-up table (LUT) that provides coarse data rate
readback values to within ±10%.
LOS Configuration
The LOS detector output, LOS Pin 22, can be configured as
either active high or active low. If CTRLC[2] is set to Logic 0
(default), the LOS pin is active high when a loss of signal
condition is detected. Writing a 1 to CTRLC[2] configures
the LOS pin to be active low when a loss of signal condition
is detected.
Initiate Frequency Acquisition
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I
frequency acquisition while keeping the ADN2817/ADN2818
in the operating mode that it was previously programmed to in
the CTRLA, CTRLB, CTRLC, CTRLD, and CTRLE registers.
Rate Selectivity
The ADN2817/ADN2818 can operate in a limited range mode
in situations where the user wants to restrict the data rates to
which the device can lock. In this mode, the frequency
acquisition range of the device is limited to a specific range of
data rates. The acquisition range is determined by program-
ming an upper and lower 9-bit code into the HI_CODE[8:1],
LO_CODE[8:1], and CODE_LSB[1:0] I
for a look-up table (LUT) showing the correct register settings
for each data rate. Table 17 has three columns, one titled Code,
one titled High Limit, and one titled Low Limit. The user
programs the code value for the high limit data rate into
HI_CODE and the code value for the low limit data rate into
LO_CODE to set the appropriate range.
For example, if the user wants to limit the acquisition range of
the ADN2817/ADN2818 to lock between 1 Gbps and 1.25 Gbps,
the following steps must be taken:
1.
2.
3.
4.
Double Data Rate Mode
Setting CTRLE = 0x02 puts the ADN2817/ADN2818 clock
output through divide-by-two circuitry allowing direct
interfacing to FPGAs that support data clocking on both rising
and falling edges.
Find the first code in Table 17 that corresponds to a data
rate below 1.0 Gbps in the low limit column, that is,
Code 236 or b011101100. Set LO_CODE[8:1] = b01110110
(LO_CODE[0] is set in Register Bit CODE_LSB[0].)
Find the first code in Table 17 that corresponds to a data
rate above 1.25 Gbps in the high limit column, that is,
Code 258 or b100000010. Set HI_CODE[8:1] = b10000001
(HI_CODE[0] is set in Register Bit CODE_LSB[1].)
Set CODE_LSB = b00000000 given that the HI_CODE[0]
= 0 and LO_CODE[0] = 0.
When there is a valid input to the device between 1.0 Gbps
and 1.25 Gbps, write a 1 to 0 transition into CTRLB[5] to
initiate a new frequency acquisition.
2
C Register Bit CTRLB[5]. This initiates a new
ADN2817/ADN2818
2
C registers. See Table 17