LTC2617 Linear Technology Corporation, LTC2617 Datasheet - Page 14

• Manufacturer Part Number: LTC2617
• Description: Ltc2617 - 14-bit Dual Rail-to-rail With I2c Interface
• Manufacturer: Linear Technology Corporation

LTC2607/LTC2617/LTC2627
OPERATIO
Table 1. Slave Address Map
27 selectable addresses for the part. The slave address
assignments are shown in Table 1.
In addition to the address selected by the address pins, the
parts also respond to a global address. This address
allows a common write to all LTC2607, LTC2617 and
LTC2627 parts to be accomplished with one 3-byte write
transaction on the I
on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.
14
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
GND
GND
GND
GND
GND
GND
GND
GND
CA2
GND
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
GLOBAL ADDRESS
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
GND
GND
GND
GND
GND
GND
GND
GND
GND
CA1
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
U
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
GND
GND
GND
GND
GND
GND
GND
GND
GND
CA0
V
V
V
V
V
V
V
V
V
2
CC
CC
CC
CC
CC
CC
CC
CC
CC
C bus. The global address is a 7-bit
SA6 SA5 SA4 SA3 SA2 SA1 SA0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF, as these pins are driven
during address detection to determine if they are floating.
Write Word Protocol
The master initiates communication with the LTC2607/
LTC2617/LTC2627 with a START condition and a 7-bit slave
address followed by the Write bit (W) = 0. The LTC2607/
LTC2617/LTC2627 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
address of the parts (set by CA0, CA1 and CA2) or the global
address. The master then transmits three bytes of data. The
LTC2607/LTC2617/LTC2627 acknowledges each byte of
data by pulling the SDA line low at the 9th clock of each data
byte transmission. After receiving three complete bytes of
data, the LTC2607/LTC2617/LTC2627 executes the com-
mand specified in the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2607/LTC2617/LTC2627 do
not acknowledge the extra bytes of data (SDA is high
during the 9th clock).
The format of the three data bytes is shown in Figure 3. The
first byte of the input word consists of the 4-bit command
word C3-C0, and 4-bit DAC address A3-A0. The next two
bytes consist of the 16-bit data word. The 16-bit data word
consists of the 16-, 14- or 12-bit input code, MSB to LSB,
followed by 0, 2 or 4 don’t care bits (LTC2607, LTC2617
and LTC2627 respectively). A typical LTC2607 write trans-
action is shown in Figure 4.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 2. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register into
the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path and
registers are shown in the Block Diagram.
26071727f