LTC2617 Linear Technology Corporation, LTC2617 Datasheet - Page 15

• Manufacturer Part Number: LTC2617
• Description: Ltc2617 - 14-bit Dual Rail-to-rail With I2c Interface
• Manufacturer: Linear Technology Corporation

OPERATIO
Table 2
COMMAND*
ADDRESS*
A3
0
0
1
*Command and address codes not shown are reserved and should not be used.
Power-Down Mode
For power-constrained applications, the power-down mode
can be used to reduce the supply current whenever one or
both of the DAC outputs are not needed. When in power-
down, the buffer amplifiers, bias circuits and reference input
are disabled and draw essentially zero current. The DAC out-
puts are put into a high impedance state, and the output pins
are passively pulled to V
Input-register and DAC-register contents are not disturbed
during power-down.
Either or both DAC channels can be put into power-down
mode by using command 0100
appropriate DAC address. The 16-bit data word is
C3 C2 C1 C0
0
0
0
0
1
A2 A1 A0
0
0
0
1
1
0
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
U
Write to Input Register
Update (Power Up) DAC Register
Write to and Update (Power Up)
Power Down
No Operation
DAC A
DAC B
All DACs
Write Word Protocol for LTC2607/LTC2617/LTC1627
Input Word (LTC2607)
Input Word (LTC2617)
Input Word (LTC2627)
C3
C3
C3
S
C2
C2
C2
SLAVE ADDRESS
REFLO
C1 C0
C1 C0
C1 C0
1ST DATA BYTE
1ST DATA BYTE
1ST DATA BYTE
b
through 90k resistors.
in combination with the
A3 A2
A3 A2
A3 A2
W
A1 A0
A1 A0
A1 A0
A
1ST DATA BYTE
D15
D13
D11
D14
D12
D10
D13
D11
D9
A
2ND DATA BYTE
2ND DATA BYTE
2ND DATA BYTE
Figure 3
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D10 D9 D8
2ND DATA BYTE
D8
INPUT WORD
D7 D6
ignored. The supply and reference currents are reduced
by approximately 50% for each DAC powered down; the
effective resistance at REF (Pin 9) rises accordingly,
becoming a high-impedance input (typically > 1GΩ)
when both DACs are powered down.
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 2
or performing an asychronous update (LDAC) as
described in the next section. The selected DAC is powered
up as its voltage output is updated. When a DAC in
powered-down state is powered up and updated, normal
settling is delayed. If one of the two DACs is in a powered-
down state prior to the update command, the power up
delay is 5µs. If on the other hand, both DACs are powered
down, the main bias generation circuit has been automati-
cally shut down in addition to the DAC amplifiers and
reference input and so the power up delay time is
Asynchronous DAC Update Using LDAC
In addition to the update commands shown in Table 2, the
LDAC pin asynchronously updates the DAC registers with
the contents of the input registers. Asynchronous update
is disabled when the input word is being clocked into
the part.
12µs (for V
D7 D6 D5 D4 D3 D2 D1 D0
D5 D4 D3 D2 D1 D0
LTC2607/LTC2617/LTC2627
A
3RD DATA BYTE
CC
= 5V) or 30µs (for V
3RD DATA BYTE
3RD DATA BYTE
3RD DATA BYTE
A
P
X
X
D1 D0
X
X
2607 F03
X
X
CC
= 3V)
15
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