LTC2617 Linear Technology Corporation, LTC2617 Datasheet - Page 16

• Manufacturer Part Number: LTC2617
• Description: Ltc2617 - 14-bit Dual Rail-to-rail With I2c Interface
• Manufacturer: Linear Technology Corporation

LTC2607/LTC2617/LTC2627
OPERATIO
If a complete input word has been written to the part, a low
on the LDAC pin causes the DAC registers to be updated
with the contents of the input registers.
If the input word is being written to the part, a low going
pulse on the LDAC pin before the completion of three bytes
of data powers up the DACs but does not cause the outputs
to be updated. If LDAC remains low after a complete input
word has been written to the part, then LDAC is recog-
nized, the command specified in the 24-bit word just
transferred is executed and the DAC outputs updated.
The DACs are powered up when LDAC is taken low,
independent of any activity on the I
If LDAC is low at the falling edge of the 9th clock of the 3rd
byte of data, it inhibits any software power-down
command that was specified in the input word. LDAC is
disabled when tied high.
Voltage Output
Both of the two rail-to-rail amplifiers have guaranteed load
regulation when sourcing or sinking up to 15mA at 5V
(7.5mA at 3V).
Load regulation is a measure of the amplifiers’ ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is
expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers’ DC output
impedance is 0.035Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output
devices; e.g., when sinking 1mA, the minimum output
voltage = 30Ω • 1mA = 30mV. See the graph Headroom
at Rails vs Output Current in the Typical Performance
Characteristics section.
The amplifiers are stable driving capacitive loads of up to
1000pF.
16
U
2
C bus.
Board Layout
The excellent load regulation performance is achieved in
part by separating the signal and power grounds as REFLO
and GND pins, respectively.
The PC Board should have separate areas for the analog
and digital sections of the circuit. This keeps the digital
signals away from the sensitive analog signals and facili-
tates the use of separate digital and analog ground planes
that have minimal interaction with each other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground. Ideally, the
analog ground plane should be located on the component
side of the board, and should be allowed to run under the
part to shield it from noise. Analog ground should be a
continuous and uninterrupted plane, except for necessary
lead pads and vias, with signal traces on another layer.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground. Resistance from the GND pin to the analog power
supply return should be as low as possible. Resistance
here will add directly to the channel resistance of the
output device when sinking load current. When a zero
scale DAC output voltage of zero is required, the REFLO pin
should be connected to system star ground. Any shared
trace resistance between REFLO and GND pins is undesir-
able since it adds to the effective DC output impedance
(typically 0.035Ω) of the part.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.
Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in
Figure 5b. Similarly, limiting can occur near full scale
when the REF pin is tied to V
full-scale error (FSE) is positive, the output for the highest
codes limits at V
limiting will occur if V
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting
can occur.
CC
as shown in Figure 5c. No full-scale
REF
is less than V
CC
. If V
REF
= V
CC
CC
– FSE.
and the DAC
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