MBM29LV002TC-70 Meet Spansion Inc., MBM29LV002TC-70 Datasheet - Page 20

• Manufacturer Part Number: MBM29LV002TC-70
• Description: Flash Memory Cmos 2m 256k ? 8 Bit
• Manufacturer: Meet Spansion Inc.

20
MBM29LV002TC
In Progress
Exceeded
Time Limits
Write Operation Status
*1 : Performing successive read operations from any address will cause DQ
*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”
Notes: • DQ
DQ
Data Polling
The MBM29LV002TC/BC devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ
Algorithm, an attempt to read the device will produce the true data last written to DQ
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ
for Data Polling (DQ
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29LV002TC/BC data pins (DQ
enable (OE) is asserted low. This means that the devices are driving status information on DQ
of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the
DQ
operation and DQ
to DQ
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See “Hardware Sequence Flags” in ■ FUNCTIONAL DESCRIPTION.)
See “ (6) AC Waveforms for Data Polling during Embedded Algorithm Operations” in ■ TIMING DIAGRAM for
the Data Polling timing specifications and diagrams.
7
at the DQ
7
• DQ
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm
0
will be read on the successive read attempts.
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Suspended
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Suspended
Mode
2
0
4
bit. However, successive reads from the erase-suspended sector will cause DQ
and DQ
is Fujitsu internal use only.
7
has a valid data, the data outputs on DQ
7
1
) is shown in “Data Polling Algorithm” in ■ FLOW CHART.
are reserve pins for future use.
Erase Suspend Read
(Erase Suspended Sector)
Erase Suspend Read
(Non-Erase Suspended Sector)
Erase Suspend Program
(Non-Erase Suspended Sector)
Erase Suspend Program
(Non-Erase Suspended Sector)
Status
-70/-90
Retired Product DS05-20863-5E_July 26, 2007
Hardware Sequence Flags
/MBM29LV002BC
6
to DQ
7
7
) may change asynchronously while the output
. Upon completion of the Embedded Program
0
may be still invalid. The valid data on DQ
Data
DQ
DQ
DQ
DQ
DQ
6
0
1
0
to toggle.
7
7
7
7
7
7
-70/-90
output. Upon completion of the
Toggle*
Toggle
Toggle
Toggle
Toggle
Toggle
Data
DQ
1
6
7
. During the Embedded
7
1
output. The flowchart
Data Data
DQ
0
0
0
0
1
1
1
2
5
to toggle.
7
DQ
at one instant
0
1
0
0
0
1
0
3
Toggle
Toggle
Data
DQ
N/A
N/A
1*
1
1
2
2
7