MBM29LV160TM-BM90 Meet Spansion Inc., MBM29LV160TM-BM90 Datasheet - Page 26

• Manufacturer Part Number: MBM29LV160TM-BM90
• Description: Flash Memory Cmos 16 M 2m ? 8/1m ? 16 Bit Mirrorflashtm*
• Manufacturer: Meet Spansion Inc.

26
MBM29LV160TM/BM
DQ
Toggle Bit I
DQ
Exceeded Timing Limits
DQ
Sector Erase Timer
Algorithm operation and DQ
on DQ
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algo-
rithm, Erase Suspend mode or sector erase time-out.
See “Data Polling during Embedded Algorithm Operation Timing Diagram” in ■SWITCHING WAVEFORMS for
the Data Polling timing specifications and diagram.
The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data
from the devices will result in DQ
Algorithm cycle is completed, DQ
During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse
sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse
in the six write pulse sequences. The Toggle Bit I is active during the sector time out.
In programm operation, if the sector being written to is protected, the Toggle bit will toggle for about 1 μs and
then stop toggling with the data unchanged. In erase, the device will erase all the selected sectors except for
the protected ones. If all selected sectors are protected, the chip will toggle the Toggle bit for about 100 μs and
then drop back into read mode, having data kept remained.
Either CE or OE toggling will cause the DQ
Algorithm Operations” in ■SWITCHING WAVEFORMS for the Toggle Bit I timing specifications and diagram.
DQ
these conditions DQ
not successfully completed. Data Polling is the only operating function of the device under this condition. The
CE circuit will partially power down the device under these conditions. The OE and WE pins will control the
output disable functions as described in “MBM29LV160TM/BM User Bus Operations (Word Mode : BYTE = V
and “MBM29LV160TM/BM User Bus Operations (Byte Mode : BYTE = V
The DQ
this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
bit will indicate a “1”. Note that this is not a device failure condition since the device was incorrectly used. If this
occurs, reset the device with command sequence.
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates a valid erase command has been written, DQ
determine whether the sector erase timer window is still open. If DQ
has begun. If DQ
been accepted, the system software should check the status of DQ
Sector Erase command. If DQ
See “Hardware Sequence Flags”.
6
5
3
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
7
to DQ
5
failure condition may also appear if a user tries to program a non blank location without pre-erase. In
0
will be read on the successive read attempts.
3
is “0”, the device will accept additional sector erase commands. To insure the command has
5
will produce a “1”. This is a failure condition indicating that the program or erase cycle was
7
bit and DQ
7
has a valid data, the data outputs on DQ
3
were high on the second status check, the command may not have been accepted.
6
will stop toggling and valid data will be read on the next successive attempts.
6
toggling between one and zero. Once the Embedded Program or Erase
6
Retired Product DS05-20906-4E_July 31, 2007
never stop toggling. Once the device has exceeded timing limits, the DQ
90
6
to toggle. See “Toggle Bit l Timing Diagram during Embedded
3
6
3
is “1” the internally controlled erase cycle
to DQ
prior to and following each subsequent
IL
)” in ■DEVICE BUS OPERATION.
0
may still be invalid. The valid data
3
may be used to
3
will
IH
)”
5