MBM29LV160TM-BM90 Meet Spansion Inc., MBM29LV160TM-BM90 Datasheet - Page 28

• Manufacturer Part Number: MBM29LV160TM-BM90
• Description: Flash Memory Cmos 16 M 2m ? 8/1m ? 16 Bit Mirrorflashtm*
• Manufacturer: Meet Spansion Inc.

28
MBM29LV160TM/BM
RY/BY
Ready/Busy
Word/Byte Configuration
Data Protection
The device provides a RY/BY open-drain output pin to indicate to the host system that the Embedded Algorithms
are either in progress or has been completed. If the output is low, the device is busy with either a program or
erase operation. If the output is high, the device is ready to accept any read/write or erase operation. If the
device is placed in an Erase Suspend mode, the RY/BY output will be high, by means of connecting with a pull-
up resister to V
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. See “RY/BY Timing Diagram during Program/Erase Operation Timing
Diagram”, “RESET Timing Diagram ( Not during Embedded Algorithms )” and “RESET Timing Diagram ( During
Embedded Algorithms )” in ■SWITCHING WAVEFORMS for a detailed timing diagram. The RY/BY pin is pulled
high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high, the
device operates in the word (16-bit) mode. Data is read and programmed at DQ
low, the device operates in byte (8-bit) mode. In this mode, DQ
DQ
commands are written at DQ
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transitions. During power up the device automatically reset the internal
state machine in Read mode. Also, with its control register architecture, alteration of memory contents only
occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
(1) Low V
To avoid initiation of a write cycle during V
than V
Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the V
is greater than V
unintentional writes when V
If Embedded Erase Algorithm is interrupted, the intervened erasing sector(s) is(are) not valid.
(2) Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
(3) Logical Inhibit
Writing is inhibited by holding any one of OE = V
be a logical zero while OE is a logical one.
(4) Power-up Write Inhibit
Power-up of the devices with WE = CE = V
The internal state machine is automatically reset to read mode on power-up.
(5) Sector Protection
Device user is able to protect each sector group individually to store and protect data. Protection circuit voids
both write and erase commands that are addressed to protected sectors.
Any commands to write or erase addressed to protected sector are ignored .
14
to DQ
LKO
. If V
CC
8
Write Inhibit
bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence
CC
CC
< V
LKO
.
. It is the user’s responsibility to ensure that the control pins are logically correct to prevent
LKO
, the command register is disabled and all internal program/erase circuits are disabled.
CC
7
is above V
to DQ
0
Retired Product DS05-20906-4E_July 31, 2007
and DQ
LKO
CC
90
IL
.
and OE = V
power-up and power-down, a write cycle is locked out for V
15
to DQ
IL
, CE = V
8
bits are ignored.
IH
will not accept commands on the rising edge of WE.
IH
, or WE = V
15
/A
-1
pin becomes the lowest address bit, and
IH
. To initiate a write, CE and WE must
15
to DQ
0
. When this pin is driven
CC
power-up
CC
CC
CC
level
less
.