MBM29PL160TD Fujitsu Microelectronics, Inc., MBM29PL160TD Datasheet - Page 22

• Manufacturer Part Number: MBM29PL160TD
• Description: 16m 2m X 8/1m X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

22
MBM29PL160TD
Low V
Write Pulse “Glitch” Protection
Logical Inhibit
Power-up Write Inhibit
To avoid initiation of a write cycle during V
than 2.3 V (typically 2.4 V). If V
are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be
erased again prior to programming.
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.
Writing is inhibited by holding any one of OE = V
be a logical zero while OE is a logical one.
Power-up of the devices with WE = CE = V
The internal state machine is automatically reset to read mode on power-up.
CC
CC
Write Inhibit
level is greater than V
LKO
CC
. It is the users responsibility to ensure that the control pins are logically correct
< V
-75/-90
LKO
, the command register is disabled and all internal program/erase circuits
CC
is above 2.3 V.
CC
IL
and OE = V
power-up and power-down, a write cycle is locked out for V
/MBM29PL160BD
IL
, CE = V
IH
will not accept commands on the rising edge of WE.
IH
, or WE = V
IH
. To initiate a write, CE and WE must
-75/-90
CC
less