MBM30LV0064 Fujitsu Microelectronics, Inc., MBM30LV0064 Datasheet
MBM30LV0064
Available stocks
Related parts for MBM30LV0064
MBM30LV0064 Summary of contents
Page 1
... The I/O pins are utilized for both address and data input/ output as well as command inputs. The MBM30LV0064 is an ideal solution for applications requiring mass non- volatile storage such as solid state file storage, digital recording, image file memory for still cameras, and other uses which require high density and non-volatile storage ...
Page 2
... MBM30LV0064 FEATURES • 3.3 V-only operating voltage (2 3.6 V) Minimizes system level power requirements • Organization Memory Cell Array : (8M + 256K) 8 bit Data Register : (512 + 16) 8 bit • Automatic Program and Erase Page Program : (512 + 16) Byte Block Erase : (8K + 256) Byte • 528 Byte Page Read Operation Random Access : 7 s (Max ...
Page 3
... I/O3 Vss 22 23 FPT-44P-M07 MBM30LV0064 TOP VIEW Vcc 44 Vcc R N.C. 39 N.C. N.C. 38 N.C. N.C. 37 N.C. N.C. 36 N.C. N. N.C. N.C. 31 N.C. N.C. 30 N.C. N.C. N.C. 29 N.C. 28 N.C. N.C. 27 I/O7 I/O7 26 I/O6 I/O6 25 I/O5 I/O5 24 ...
Page 4
... MBM30LV0064 PIN DESCRIPTIONS Pin Number Pin Name Data Input/Output I/O0 to The I/O ports are used for transferring command, address, and input/output data into I/O7 and out of the device. The I/O pins will be high impedance when the outputs are dis- abled or the device is not selected. ...
Page 5
... BLOCK DIAGRAM High Voltage Pumps ALE CLE SE WP State Machine Command Register Address Register Status Register MBM30LV0064 Y-Decoder Data Register & S/A Memory Array Data Register & S/A Y-Decoder I/O Register & Buffer R/B I/O0 to I/O7 5 ...
Page 6
... MBM30LV0064 SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT The Program operation is implemented in page units while the Erase operation is carried out in block units. Register Memory Cell Array I/O0 First Cycle A 0 Second Cycle A 9 Third Cycle column address page address ...
Page 7
... Read Mode Operation Status * ALE MBM30LV0064 ...
Page 8
... MBM30LV0064 COMMAND OPERATION Function Read (1) Read (2) Read (3) Sequential Data Input Page Program Block Erase Reset Status Read ID Read *1: The 00h Command defines starting Address on the 1st half Page. *2: The 01h Command defines starting Address on the 2nd half Page. *3: The 50h Command is valid only When SE is low level. ...
Page 9
... The Read (1), (2) mode is invoked by latching the 00h or 01h command into the command register. This mode (00h) will be automatically selected when the device powers up. CE CLE ALE WE RE R/B I/O0 to I/O7 Command 01h 00h Page (Row) X Address Figure 2 Starting Address 255 511 527 Y Y (Column Address) Read Mode (1), (2) Operation MBM30LV0064 = 0 while 01h sets Data Output 9 ...
Page 10
... MBM30LV0064 Read (3): 50h The Read (3) mode has identical timing to that of Read (1) and (2). However, while Read (1) and (2) are used to access the array, Read (3) is used to access the 16 byte spare area. When the 50h command is executed, the pointer will be set to an address space between columns 512 and 527. The values of Y will complete the address decoding. During this operation, only address bits A address ...
Page 11
... Upon completion, the Status Register bit I/O0 should be used to verify a successful erase. R/B I/O0 to I/O7 60h 10h Figure 5 Page Program to A are don’t care bits. Once the block address is successfully loaded Address Input D0h Figure 6 Block Erase MBM30LV0064 70h I/ Pass 1 = Fail 70h I/ Pass 1 = Fail 11 ...
Page 12
... MBM30LV0064 Read ID: 90h This mode allows the identification of the manufacturer and product. After the 90h command cycle, one address cycle follows in which 00h is entered. The next two RE pulses will output the manufacturer and device code respectively. RE I/O0 to I/O7 90h I/O7 Manufacturer 0 Device 1 Status Read: 70h The Status Register may be used to determine if the device is ready, in the write protect mode, or passed program/erase operations ...
Page 13
... Status Register will be set to C0h reset command is issued while the device is in the reset state, the command will be ignored. If the device is reset during the program or erase operations, the internal high voltages will be discharged before R/B goes high. R/B I/O0 to I/O7 FFh CE(2) CE(N) Device(2) Device(N) 0/1 70h Status of Device(1) Status of Device(N) Figure 8 Status Read MBM30LV0064 8 I/O0 to I/O7 R/B 0/1 13 ...
Page 14
... MBM30LV0064 ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature with Power Applied Storage Temperature Voltage on a I/O pin with Respect to Ground * Voltage on a pin Except I/O with Respect to Ground * Power Supply Voltage *: Minimum DC voltage on input or I/O pins is 0.5V. During voltage transitions, inputs may under shoot Vss to 2.0 V for periods ns. Maximum DC voltage on input pins is V ...
Page 15
... 3 3 OUT I/O pins V IH Except I/O pins V — –400 2 0 MBM30LV0064 Value Unit Min. Typ. Max. — — — — — — — — µ ...
Page 16
... MBM30LV0064 2. AC Characteristics (Note 1) Parameter CLE Setup Time CLE Hold Time CE Setup Time CE Hold Time Write Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time WP High to WE Low Ready to RE Falling Edge ...
Page 17
... CE high time must be held for 100 ns or more when the delay time of CE with respect 200 ns (see the figure below). When the CE delay time is within 30 ns, the device is kept in the Ready state and will output no Busy signal. MBM30LV0064 Symbol t ...
Page 18
... MBM30LV0064 CE RE 525 509 R 100 ns CEH 526 527 510 511 Busy *: Busy signal is not output. ...
Page 19
... Refer to Application Note (10) toward the end of this document. *2: Refer to Application Note (13) toward the end of this document. This specification is on conditions that ECC system would be combined. VALID BLOCKS The MBM30LV0064 occasionally contains unusable blocks. Refer to Application Note (12) toward the end of this document. Parameter Valid Block Number ...
Page 20
... MBM30LV0064 TIMING DIAGRAMS CLE t CLS ALS ALE I/O0 to I/O7 Figure 9 CLE t CLS ALS ALE I/O0 to I/O7 Figure CLH ALH Command Input Cycle Timing Diagram ...
Page 21
... CLE CE t ALS ALE WE I/ GND input : input : to D 511 CC IN Figure N 527 Data Input Cycle Timing Diagram MBM30LV0064 t CLH ...
Page 22
... MBM30LV0064 I/ R/B Figure 12 CLE I/O0 to I/O7 R/B Figure REH REA REA t t RHZ RHZ Serial Read Cycle Timing Diagram t CLS t CLS t CLH CSTO t WHR 70h Status Read Cycle Timing Diagram ...
Page 23
... AR2 ALH REA OUT OUT 255 N : 256 to 511 MBM30LV0064 t CEH t CRY ** D OUT D OUT CHZ t RHZ D OUT ...
Page 24
... MBM30LV0064 t CLE CLH t CLS ALH ALE I/O0 01h to I/O7 Column address R/B **: SE = GND input : input : D CC Note: The CE signal must stay “Low” after the third address input and during Busy state. t CLE CLH t CLS ...
Page 25
... R t Page R M Page M Access 527 Sequential Read (1) Timing Diagram 256 256 256 t Page Page M Page Access Access 527 511 Sequential Read (2) Timing Diagram MBM30LV0064 ** ...
Page 26
... MBM30LV0064 CLE CE WE ALE RE I/O0 50h to I/O7 R/B **: SE = GND input : not input V Note: The CE signal must stay “Low” after the third address input and during Busy state. Figure 512 512 512 Column ...
Page 27
... Figure 22 t ALS 10h A N BERASE t WB D0h Erase Start Status Read Command Auto Block Erase Timing Diagram MBM30LV0064 t PROG Status 70h Output : Status 70h Output Command : ...
Page 28
... MBM30LV0064 CLE t CLS ALH ALE I/O0 90h to I/O7 Figure CLS t t ALH ALS AR1 00h 04h t REAID Address Input Maker Code Device Code ID Read Operation Timing Diagram E6h t REAID : ...
Page 29
... No Program Sequence Yes Continue to Program? No End Pointer Action Flow Chart MBM30LV0064 start address in 50h area in previous use, the 50h command input can be skipped. (and) 01h area in previous use, the 00h command input can be skipped. or 50h. Yes Start address 01h to 00h? ...
Page 30
... MBM30LV0064 (3) Acceptable commands after serial input command ‘80h’ When the serial input command (80h) is input for program execution, commands other than the program execution command (10h) or reset command (FFh) should not be input Address input R/B Figure command other than ‘10h’ or ‘FFh’ is input, the program operation is not performed. ...
Page 31
... After power-off, each input signal level may be undefined. Use the WP signal as shown in the figure below. 2 DON’T CARE CE, WE, RE CLE, ALE Device R (Max.) — 3 Figure 28 Termination for R Operation Figure 29 Power On/Off Sequence MBM30LV0064 by a resistor. CC DON’T CARE ...
Page 32
... MBM30LV0064 (8) Setup for WP Signal A Low-level WP signal will force erasing and programming to be reset. To control, use the WP signal as shown below. Program WE DIN WP R/B Program Prohibition WE DIN WP R/B Erase WE DIN WP R/B Erase Prohibition WE DIN WP R 100 ns (Min 100 ns (Min 100 ns (Min.) ...
Page 33
... Internal read operation starts when WE in the third cycle goes high. Figure 30 Program operation CLE CE WE ALE 80h I/O0 to I/O7 Figure 31 Program Operation when 4 Address Cycles are Input Address input Read Operation when 4 Address Cycles are Input Address input ignored MBM30LV0064 ignored Data input 33 ...
Page 34
... MBM30LV0064 (10) Divided programming on same page The device uses the page programming method that allows programming up to ten times on the same page. The procedure for divided programming (programming on a part of one page) is shown below. The first programming Column A Page N Data Pattern 1 The second programming ...
Page 35
... If an error occurs at erasing, like programming, remedies should be executed on a system basis to prevent access to blocks causing the error. Some MBM30LV0064 products have invalid blocks (bad blocks) at shipping. After mounting the device in the system, test whether there are no bad blocks. If there are any bad blocks, they should not be accessed ...
Page 36
... MBM30LV0064 (14) ALE Input Condition during Address Input The ALE input must remain high once asserted until the last address byte has been written to the device. Read Operation CLE CE WE ALE I/O0 to I/O7 Program Operation CLE CE WE ALE I/O0 to I/O7 Erase Operation CLE CE WE ALE I/O0 to I/O7 36 ...
Page 37
... When the last byte in the last page of the device is read, the internal address counter will wrap around to the fist page in the device. Toggling X times ( Inhibiting) Starting Address Y Inhibit toggling 10h MBM30LV0064 Start from column address Output 70h Status : Invalid Data IL 37 ...
Page 38
... MBM30LV0064 (18) CE don’t care timing for read and program operation CE can be don’t-care (“H” or “L”) state during read and program operation as follows. <Read Operation> I/ Command I/O7 R/B (55 ns Max.) t CEA CE t REA RE I/O0 to I/O7 <Program Operation> ...
Page 39
... BAD BLOCK TEST FLOW Block No. = Block No Yes Figure 36 MBM30LV0064 Test Start Block No Page 1 & Set as a bad block Blank Check ] ^ All FFh? Yes > B No. 511 = No Test End Bad Block Test Flow 39 ...
Page 40
... Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM30LV0064 -PFTN DEVICE NUMBER/DESCRIPTION MBM30LV0064 64 Mega-bit (8M 2 3.6 V Read, Write, and Erase Valid Combinations MBM30LV0064 40 PACKAGE TYPE PFTN = 44-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR = 44-Pin Thin Small Outline Package (TSOP) Reverse Pinout 8-Bit) CMOS Flash Memory ...
Page 41
... M –0.05 –.002 (Mounting height) 0.50±0.10 0(0)MIN (.020±.004) (STAND OFF) MBM30LV0064 0.15(.006) 0.25(.010) 0.15(.006)MAX 0.40(.016)MAX 11.76±0.20 (.463±.008) 10.16±0.10 (.400±.004) 0.15±0.05 (.006±.002) 10.76±0.20 (.424±.008) Dimensions in mm (inches) (Continued) ...
Page 42
... MBM30LV0064 (Continued) 44-pin plastic TSOP (II) (FPT-44P-M08 INDEX LEAD No 16.80(.661)REF 0.80(.0315)TYP 0.10(.004) 0.30±0.10 0.13(.005) (.012±.004) * 18.41±0.10 (.725±.004) 2000 FUJITSU LIMITED F44017S-1C Resin protrusion. (Each side: 0.15(.006) Max Details of "A" part "A" 0(0)MIN 0.50± ...
Page 43
... MBM30LV0064 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. ...