S3032 AMCC (Applied Micro Circuits Corp), S3032 Datasheet - Page 3

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S3032

Manufacturer Part Number
S3032
Description
Sonet/sdh/atm OC-3/12 Transceiver W/cdr
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet

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Figure 4. S3033 Transceiver Functional Block Diagram
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
April 7, 2000 / Revision D
REFCLKP/N
RSCLKP/N
TSCLKP/N
RLPTIME
SLPTIME
TSTRST
MODE0
MODE1
TTLREF
SDPECL
RSDP/N
PIN[7:0]
SDTTL
PICLK
RSTB
DLEB
Receiver
LLEB
OOF
Transmitter
M
U
X
8
CAP1
8:1 PARALLEL
TO SERIAL
SYNTHESIZER
CLOCK
CAP2
TIMING
GEN
TO PARALLEL
1:8 SERIAL
DECISION
DETECT
FRAME
BYTE
CKT
D
TIMING
GEN
8
TSCLKP/N
TSDP/N
PCLK
19MHZCLK
POUT[7:0]
POCLK
FP
Suggested Interface Devices
S3033 OVERVIEW
The S3033 transceiver implements SONET/SDH se-
rialization/deserialization, transmission, and frame
detection/recovery functions. The block diagram in
Figure 4 shows the basic operation of the chip. This
chip can be used to implement the front end of
SONET equipment, which consists primarily of the
serial transmit interface and the serial receive inter-
face. The chip handles all the functions of these two
elements, including parallel-to-serial and serial-to-par-
allel conversion, clock generation, and system
timing. The system timing circuitry consists of man-
agement of the data stream, framing, and clock
distribution throughout the front end.
The S3033 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:
Transmitter Operations:
Receiver Operations:
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figures 7 through 10.
A
A
A
1. 8-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
1. Frame detection
2. Serial-to-parallel conversion
3. 8-bit parallel output
M
M
M
C
C
C
C
C
C
S
C
S (
N
S (
3
O
L I
1
1
0
N
2
E
2
2
0
0
G
4
) 1
) 2
O
1
P
A
5
O
T
5
M
S
6 /
A /
S
2
2
T
O
M
M
N
E
b
S
s p
T
O
M
N
C
E
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p
T
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S3033
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3

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