S3045 AMCC (Applied Micro Circuits Corp), S3045 Datasheet - Page 4

• Manufacturer Part Number: S3045
• Description: S3045 Sonet/sdh Oc-48 to Oc-12 Mux/demux Evaluation Board
• Manufacturer: AMCC (Applied Micro Circuits Corp)

S3045
SONET/SDH OC-48 TO OC-12 MUX/DEMUX EVALUATION BOARD
The user may vary VBB Bias (JP8) to terminate the S3045 Evaluation Board to different bias levels (VBB or
ground) as shown in Table 2. AC termination is part of the S3042 and S3040 inputs.
The user has the option of using one, both, or none of the on board clock recovery units (S3040).
The user can choose one of the following reference clock options for the S3040’s:
1.An external single ended 155MHz (Default factory configuration).
2.An external differential 155 MHz (Must be configured at the factory for this option).
3.The on board 155MHz oscillator (Must be configured at the factory for this option).
JP1 and JP2 of the S3045 Evaluation Board must be configured as in Table 2 for the desired clock option.
SMA Edge Connectors.
SMA edge connectors are provided for the differential serial input/output signals and output clock. All interfaces
to the S3045 Evaluation Board are AC coupled, 50 Ohms.
S3040 #1
Serial Data In [SERDATIP/N] (J5, J6) – (Internal Termination.) Clock is recovered from the transitions on these
inputs. J6 is not installed for a single-ended configuration.
Serial Data Out [SERDATOP/N] (J13, J14) – This signal is the delayed version of the incoming data stream
(SERDATIP/N) updated on the falling edge of Serial Clock Out (SERCLKOP).
Serial Clock Out [SERCLKOP/N] (J15, J16) –This signal is phase aligned with Serial Data Out (SERDATOP/N).
S3040 #2
Serial Data In [SERDATIP/N] (J7, J8) – (Internal Termination.) Clock is recovered from the transitions on these
inputs.
Serial Data Out [SERDATOP/N] (J17, J18) – This signal is the delayed version of the incoming data stream
(SERDATIP/N) updated on the falling edge of Serial Clock Out (SERCLKOP).
Serial Clock Out [SERCLKOP/N] (J19, J20) – This signal is phase aligned with Serial Data Out (SERDATOP/N).
S3041
Transmit Clock Output [TSCLKP/N] (J11, J12) – Transmit serial clock that can be used to retime the TSD
signal. An optical transmitter can use the rising edge of TSCLK to retime the TSD data.
Transmit Serial Data [TSDP/N] (J9, J10) – Serial data stream signals, normally connected to an optical
transmitter module.
S3042
Receive Serial Data [RSDP/N] (J1, J2) – Serial data streams normally connected to an optical module. These
inputs are clocked by the rising edge RSCLKP inputs. The RSD will be frame aligned and demultiplexed to an 8-
bit parallel output <7:0>. J2 is not installed for a single-ended configuration.
Receive Serial Clock [RSCLKP/N] (J3, J4) – Recovered clock signal that is synchronous with the RSDP/N
inputs. This clock is used by the receive section as the master clock to perform framing and deserialization
functions. J4 is not installed for a single-ended configuration.
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