S3092 AMCC (Applied Micro Circuits Corp), S3092 Datasheet - Page 7

• Manufacturer Part Number: S3092
• Description: Sonet/sdh/atm OC-192 1:16 Receiver With CDR And Postamp
• Manufacturer: AMCC (Applied Micro Circuits Corp)

S3092 – SONET/SDH/ATM OC-192 1:16
Receiver with CDR and Postamp
S3092 ARCHITECTURE/FUNCTIONAL
DESIGN
Receiver Description
The S3092 receiver chip provides the first stage of the
digital processing of a receive SONET STS-192 bit-
serial stream. It converts the bit-serial 9.953 Gbps to
10.709 Gbps data stream into a 622.08 Mbps to
669.33 Mbps 16-bit parallel data format. See Table 17
for Reference Clock (REFCLK) required.
Postamp
The S3092 limiting postamp takes the differential
serial data from the SERDATIP/N pins and provides
36 dB small signal gain. The input to the postamp can
be either AC or DC coupled.
Clock Recovery
Clock recovery, as shown in the block diagram in Fig-
ure 4, generates a clock that is the same frequency as
the incoming data bit rate at the serial data input. The
clock is phase aligned by a PLL so that it samples the
data in the center of the data eye pattern.
The Clock and Data Recovery (CDR) extracts a syn-
chronous signal from the serial data input using a
frequency and Phase Lock Loop (PLL). The PLL con-
sists of a Voltage Controlled Oscillator (VCO), Phase/
Frequency Detectors (PFD), and a loop filter.
The frequency detector ensures predictable lock-up
conditions. It is used during acquisition, and serves as a
means of pulling the VCO into the range of the data rate
where the phase detector is capable of acquiring lock.
The phase detector used in the CDR is designed to
give minimum static phase error of the PLL. When a
transition has occurred, the value of the sample in the
vicinity of the transition indicates whether the VCO
clock leads or lags the incoming data. The phase
detector then produces a binary output accordingly.
When a loss-of-signal condition exists, SDN goes
inactive, and the PLL locks onto the Reference Clock
(REFCLK) to provide a steady output clock. There are
two pins (CAP1 and CAP2) to connect the external
capacitors and resistors in order to adjust the PLL loop
performance.
The phase relationship between the edge transitions
of the data and those of the generated clock are com-
pared by a phase/frequency discriminator. Output
pulses from the discriminator indicate the required
direction of phase corrections. These pulses are
smoothed by an integral loop filter. The output of the
loop filter controls the frequency of the Voltage Con-
tr ol led O scil lat or (V CO), whi ch generates t he
recovered clock.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET data
signal.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance that exceeds the minimum toler-
ance proposed for SONET equipment by the Bellcore
TA-NWT-000253 standard.
Lock Detect
The S3092 contains a lock detect circuit that monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss-of-signal or loss-of-lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than the typical
value stated in Table 6, the PLL will be declared out of
lock. The lock detect circuit will poll the input data
stream in an attempt to reacquire lock to data. If the
recovered clock frequency is determined to be within
the typical value stated in Table 6, the PLL will be
declared in lock, and the lock detect output will go
active. An inactive SDN will also cause an out-of-lock
condition.
Serial-to-Parallel Converter
The serial-to-parallel converter consists of three 16-bit
registers. The first is a serial-in, parallel-out shift regis-
ter, which performs serial to parallel conversion. The
second is a 16-bit internal holding register, which
transfers data from the serial to parallel register. On
the falling edge of the POCLK, the data in the holding
register is transferred to an output holding register
which drives POUTP/N[15:0].
Power Sequencing
In order to avoid latch up, it is required that the -5.2 V
power be applied to the S3092 for a minimum of 50 ms
before the application of 3.3 V power.
Revision A – February 22, 2002
DEVICE SPECIFICATION
7