CDS-1401 Datel, Inc., CDS-1401 Datasheet - Page 4

• Manufacturer Part Number: CDS-1401
• Description: Fast-settling Correlated Double Sampling Circuit: 14-bit
• Manufacturer: Datel, Inc.

CDS-1401
explanation in that the floating capacitor is not usually
“discharged” but, in fact, “recharged” to some predetermined
dc voltage, usually called the “reference level”. The pixel offset
appears as an output deviation from that reference level.)
The floating capacitor is normally discharged (charged) via a
shunt switch (typically a FET structure) that has a non-zero
“on” resistance. When the switch is on, its effective series
resistance exhibits thermal noise (Johnson noise) due to the
random motion of thermally energized charge. Because the
shunt switch is in parallel with the floating capacitor, the
instantaneous value of the thermal noise (expressed in either
Volts or electrons) appears across the cap. When the shunt
switch is opened, charge/voltage is left on the floating cap.
The magnitude of this “captured noise voltage” is a function of
absolute temperature (T), the value of the floating capacitor (C)
and Boltzman’s constant (k). It is commonly referred to as
“kTC” noise.
The second contributor to the constantly varying pixel offsets
is the fact that, at high pixel rates, the floating capacitor never
has time to fully discharge (charge) during the period in which
its shunt switch is closed. There is always some “residual”
charge left on the cap, and the amount of this charge varies
as a function of what was the total charge held during the
previous pixel. This amount of residual charge is, in fact,
deterministic (if you know the previous charge and the number
of time constants in the discharge period), however, it is less
of a contributor than kTC noise.
The third major contributor to pixel offset is the fact that as the
shunt FET is turned off, the voltage across (and the charge
A/D CLOCK 1 (Pin 17)
A/D CLOCK 1 (Pin 18)
A/D CLOCK 2 (Pin 19)
A/D CLOCK 2 (Pin 20)
FOR CDS (Pins 3 and
VOLTAGE OUTPUT
ANALOG INPUT
(CCD OUTPUT)
S/H 1 (Pin 11)
S/H 2 (Pin 12)
4 are tied)
NOTE: Not Drawn to Scale
RESET N
VIDEO SIGNAL N-1
Figure 2. CDS-1401 Typical Timing Diagram
OFFSET N
100ns typ.
30ns typ.
OFFSET +
VIDEO N
4
100ns typ.
30ns typ.
stored on) its parasitic junction capacitances changes. The
result is an “injection” of excess charge onto the floating cap
causing a voltage step normally called a “pedestal”.
The fourth major contributor to pixel offset is a low-frequency
noise component (usually called 1/f noise or pink noise)
associated with the CCD’s output buffer amplifier.
Due to all of these contributing factors, "pixel offsets" vary from
sample to sample in an inconsistent, unpredictable manner.
Traditional Approach to CDS
There are a number of techniques for dealing with the varying-
offset idiosyncrasy of CCD’s. The most prevalent has been
what can be called the “sample-sample-subtract” technique.
This approach requires the use of two high-speed sample-hold
(S/H) amplifiers and a difference amplifier. The first S/H is
used to acquire and hold a given pixel’s offset. Immediately
after that, the second S/H acquires and holds the same pixel’s
offset+video signal. After both the S/H outputs have fully
settled, the difference amplifier subtracts the offset from the
offset+video yielding the valid video signal.
CDS-1401 Approach (See Figure 1)
The DATEL CDS-1401 takes a slightly different, though clearly
superior, approach to CDS. It can be called the “sample-
subtract-sample” approach.
Note that the CDS-1401 has been configured to offer the
greatest amount of user flexibility. Its two S/H circuits function
independently. They have separate input and output pins.
Each has its own independent control lines. The control-line
signals are delayed, buffered, and brought back out of the
HOLD
RESET N+1
VIDEO SIGNAL N
OFFSET N+1
HOLD
VIDEO N+1
OFFSET +
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