HD49338F Renesas Electronics Corporation., HD49338F Datasheet
HD49338F
Related parts for HD49338F
HD49338F Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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... HD49338F/HF CDS/PGA & 12-bit A/D Converter Description The HD49338F/ CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 12-bit A/D converter in a single chip. Functions Correlated double sampling PGA Offset compensation Serial interface control ...
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... HD49338F/HF Pin Arrangement VRM VRT VRB OEB SDATA SCK Pin Description Pin No. Symbol Description 1 D0 Digital output (LSB D10 Digital output 12 D11 Digital output (MSB) 13 DRDV Output buffer power supply ( Digital ground (0 V) ...
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... HD49338F/HF Pin Description (cont.) Pin No. Symbol Description 32 BIAS Internal bias pin Connect a 33 kΩ resistor between BIAS and Analog power supply ( input pin 35 AV Analog ground ( ADCIN ADC input pin 37 VRM Reference voltage pin 1 Connect a 0.1 µF ceramic capacitor between VRM and AV ...
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... HD49338F/HF Input/Output Equivalent Circuit Pin Name Digital output D0 to D11 Digital input ADCLK, OBP, SPBLK, SPSIG, CS, SCK, SDATA, PBLK, OEB Analog CDSIN ADCIN Y IN BLKSH, BLKFB VRT, VRM, VRB BIAS Rev.2.00 May 20, 2005 page Equivalent Circuit DIN STBY DV Digital input Note: Only OEB is pulled down to about 70 k ...
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... HD49338F/HF Block Diagram ADCIN PBLK 26 CDSIN 26 CDS BLKSH 28 BLKC 28 DC offset BLKFB 29 compensation circuit 17 Rev.2.00 May 20, 2005 page Timing generator 12 bit PGA ADC Serial Bias interface generator OEB 11 D11 10 D10 ...
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... AMP VRT BLKFB Figure 1 HD49338F/HF Functional Block Diagram 1. CDS (Correlated Double Sampling) Circuit The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The black level is directly sampled using the SPBLK pulse, buffered by the SHAMP, then provided to the CDSAMP ...
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... HD49338F/HF 2. PGA Circuit The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain using 10 bits of register. The equation below shows how the gain changes when register value N is from 0 to 1023. In CDSIN mode: Gain = (–2. 0.033 dB) × N (LOG linear). ...
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... HD49338F/HF 6. ADC Digital Output Control Function The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5 show the output functions and the codes. Table 3 ADC Digital Output Functions ...
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... HD49338F/HF 7. Adjustment of Black-Level S/H Response Frequency Characteristics The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the register settings, as shown in table 6. Table 6 SHSW CR Time Constant Setting SHSW-fsel (Register setting) [0] [1] [ Time Constant (Typ) 2.20 nsec (cutoff frequency conversion) ...
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... HD49338F/HF Timing Chart Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used When CDSIN input mode is used N CDSIN SPBLK SPSIG ADCLK D0 to D11 N 12 When ADCIN input mode is used N+1 N ADCIN ADCLK D0 to D11 N 11 Note: The phases of SPBLK and SPSIG are those when the serial data SPinv bit is set to low. ...
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... HD49338F/HF Detailed Timing Specifications Detailed Timing Specifications when CDSIN Input Mode is Used Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing specification. CDSIN SPBLK SPSIG ADCLK D0 to D11 Note: 1. When serial data Spinv bit is set to low. (When the Spinv bit is set to high, the polarities of the SPBLK and the SPSIG are inverted ...
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... HD49338F/HF Detailed Timing Specifications at Pre-Blanking Figure 5 shows the pre-blanking detailed timing specifications. PBLK Digital output (D0 to D11) Figure 5 Detailed Timing Specifications at Pre-Blanking Detailed Timing Specifications when ADCIN Input Mode is Used Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification. ...
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... HD49338F/HF Serial Interface Specifications Table 10 Serial Data Function List Resister (LSB) Low DI 01 Low DI 02 Low PGA gain setting (LSB) * SLP PGA gain setting * STBY PGA gain setting * Output mode setting (LINV PGA gain setting * Output mode setting (MINV) ...
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... HD49338F/HF Explanation of Serial Data of CDS Part Serial data of CDS part has the following functions. PGA gain (D5 to D12 of register 0) Details are referred to page 6 block diagram. At CDS_in mode: –2. 0.132 dB × N (Log linear) At ADC_in mode: 0.57 times + 0.01784 times × N (Times linear) ∗: Full-scale digital output is defined when input. ...
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... HD49338F/HF Clamp ( register 2) Determine the OB part level with digital code of ADC output. Clamp level = setting data × Default data LSB. HGstop-Hsel, HGain-Nsel (D8 to D11 of register 2) Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch the high speed leading mode. Transfer the gain +1/– ...
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... HD49338F/HF Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss quantization) occurs to the image. Differential code and gray code are recommended for this countermeasure. ...
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... Item Power supply voltage Analog input voltage Digital input voltage Operating temperature Power dissipation Storage temperature Power supply voltage range (HD49338HF) Power supply voltage range (HD49338F) Notes indicates AV and and DV must be commonly connected outside the IC. When they are separated by a noise filter, the ...
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... HD49338F/HF Electrical Characteristics (cont.) (Unless othewide specified 25°C, AV Items for CDSIN Input Mode Item Symbol Consumption current (1) I DD1 Consumption current (2) I DD2 CCD offset tolerance range V CCD Timing specifications (1) t CDS1 Timing specifications (2) t CDS2 Timing specifications (3) t CDS3 ...
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... SPBLK Start control SPSIG of TG and ADCLK camera DSP etc. OBP HD49338F/HF serial data transfer RESET bit Automatic offset calibration The following describes the above serial data transfer. For details on registers 0, 1, and 2, refer to table 10. (1) Register 2 setting (2) Register 2 setting (3) Register 0 and 1 settings (4) Please perform an offset calibration in the period which avoided PBLK of V ...
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... At power-on, automatic adjustment of the offset voltage generated from PGA, ADC, etc., must be implemented in accordance with the power-on operating sequence (see page 16). Rev.2.00 May 20, 2005 page should be made off-chip Digital Noise filter +3. HD49338F/ and DV DD and DV are isolated by a noise filter Example of noise filter ...
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... C21 C22 0.1 0.1 0.1 0.1 0.1 0.1 C13 C12 C11 0.1 0.1 0 BLKSH 28 BLKFB 29 CDSIN 30 HD49338F/HF (CDS/PGA+ADC) BLKC 31 BIAS ADCIN C16 47/6 C17 C18 C19 C20 C21 C22 0.1 0.1 0.1 0.1 0.1 ...
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... HD49338F/HF Package Dimensions JEITA Package Code RENESAS Code P-LQFP48-7x7-0.50 PLQP0048KD Index mark Rev.2.00 May 20, 2005 page Previous Code MASS[Typ.] FP-48C/FP-48CV 0. NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...