CDS-1402 Datel, Inc., CDS-1402 Datasheet - Page 6

• Manufacturer Part Number: CDS-1402
• Description: Faster-settling Correlated Double Sampling Circuit: 14-bit
• Manufacturer: Datel, Inc.

As soon as the transients/noise associated with the charge
transport begins to decay, S/H2 can be driven into the sample
mode. S/H2 can then be left in the sample mode until just
before the reset pulse for the output capacitor.
In Figure 2, S/H's 1 and 2 both have the same acquisition time.
If the pixel-to-pixel amplitude variation of offset signals is much
less than that of video signals, it may not be necessary for the
allocated acquisition time of S/H1 to be as long as that of S/H2.
As shown in the plot (Figure 4) of acquisition times vs. input
signal step size, the S/H's internal to the CDS-1402 acquire
smaller-amplitude signals quicker than they acquire larger-
amplitude signals. In "maximum-throughput" applications,
assuming "asymmetric" timing can be accommodated, each
S/H should only be given the time it requires, and no more, to
acquire its input signal. Leaving a S/H amp in the sample
mode for a longer period of time has little added benefit.
As an example, the graph shows that it takes 32ns to acquire a
500mV step to within 10mV of accuracy and 73ns to acquire a
500mV step to within 0.5mV of accuracy. The figures in this
graph are typical values at room temperature.
The CDS-1402 brings out 4 control lines that can be used to
trigger an A/D converter connected to its output. If the A/D is a
CDS-1402
105
105
100
100
95
95
90
90
85
85
80
80
75
75
70
70
65
65
60
60
55
55
50
50
45
45
40
40
35
35
30
30
0
1
Figure 4. Acquisition Time versus Accuracy and Step Size
2
Input Step Size (Volts)
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sampling type, system timing should be such that the A/D's
input S/H amplifier is acquiring the output of the CDS-1402 at
the same time the output is settling to its final value.
For most sampling A/D's, the rising edge of the start-convert
pulse drives the internal S/H into the hold mode under the
assumption the S/H has already fully acquired and is tracking
the input signal. In this case, the same edge can not be used
to drive S/H2 into the hold mode and simultaneously initiate
the A/D conversion. The output of S/H2 needs time to settle its
sample-to-hold switching transient, and the input S/H of the
A/D needs time to fully acquire its new input signal.
As shown in Figure 1, output line A/D CLOCK1 (pin 18) is a
slightly delayed version of the signal applied to pin 11 (S/H1
COMMAND), and A/D CLOCK1 (pin 17) is its complement.
A/D CLOCK2 (pin 19) is a delayed version of the signal applied
to pin 12 (S/H2 COMMAND), and A/D CLOCK2 (pin 20) is its
complement. Any one of these signals, as appropriate, may be
used to trigger the A/D conversion.
Figure 3 is a typical timing diagram for a CDS-1402 in front of
DATEL's 14-bit, 5MHz sampling A/D, the ADS-944.
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1mV accuracy
2mV accuracy
5mV accuracy
10mV accuracy
±1mV accuracy
±0.5mV accuracy
±2mV accuracy
±5mV accuracy
±10 mV accuracy
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