IDT82P2288 Integrated Device Technology, Inc., IDT82P2288 Datasheet - Page 336

• Manufacturer Part Number: IDT82P2288
• Description: 8 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2288
E1 TPLC Configuration (0CBH, 1CBH, 2CBH, 3CBH, 4CBH, 5CBH, 6CBH, 7CBH)
SIGSNAP:
the signaling bits of the current whole Signaling Multi-frame.
GSTRKEN:
timeslot.
51~5FH).
GSUBST[2:0]:
E1 TPLC Control Enable (0CCH, 1CCH, 2CCH, 3CCH, 4CCH, 5CCH, 6CCH, 7CCH)
PCCE:
Programming Information
GSUBST[2:0]
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
This bit is valid when the Signaling Multi-frame is generated.
= 0: Disable the signaling snapshot.
= 1: Enable the signaling snapshot. That is, the signaling bits of the first Basic frame are locked and input on the TSIGn/MTSIGA(MTSIGB) pin as
= 0: The replacement is performed on a per-timeslot basis by setting the STRKEN bit (b4, E1-ID-41~4FH & 51~5FH) in the corresponding
= 1: The signaling bits (ABCD) of all timeslots are replaced by the signaling trunk conditioning code in the A,B,C,D bits (b3~0, E1-ID-41~4FH &
These bits select the replacement of all the channels.
= 0: Disable all the functions in the Transmit Payload Control.
= 1: Enable all the functions in the Transmit Payload Control.
others
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
The replacement is performed on a per-timeslot basis by setting the SUBST[2:0] bits (b7~5, E1-ID-00~1FH) in the corresponding timeslot.
The data of all timeslots is replaced by the data trunk code set in the DTRK[7:0] bits (b7~0, E1-ID-20~3FH).
The data of all timeslots is replaced by the A-Law digital milliwatt pattern.
The data of all timeslots is replaced by the µ-Law digital milliwatt pattern.
The data of all timeslots is replaced by the payload loopback code extracted from the Elastic Store Buffer in the receive path.
Reserved.
SIGSNAP
R/W
7
1
7
GSTRKEN
R/W
6
0
6
5
5
Reserved
Reserved
4
Replacement Selection
4
325
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3
3
GSUBST2
R/W
2
0
2
GSUBST1
R/W
1
0
1
March 22, 2004
GSUBST0
PCCE
R/W
R/W
0
0
0
0