IDT82P2288 Integrated Device Technology, Inc., IDT82P2288 Datasheet - Page 57

• Manufacturer Part Number: IDT82P2288
• Description: 8 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2288
than 5 bytes (including the FCS, excluding the flags);
ber of octets;
(The address comparison mode is selected by the ADRM[1:0] bits. If
high byte address comparison is required, the high byte address posi-
tion (the byte following the opening flag) is compared with the value in
the HA[7:0] bits, or with ‘0xFC’ or ‘0xFE’. Here the ‘C/R’ bit position is
excluded to compare. If low byte address comparison is required, the
high byte address position is compared with the value in the LA[7:0] bits.
DAT[7:0] bits. When the overhead is read from the FIFO, it will be indi-
cated by the PACK bit. When all valid HDLC blocks are pushed into the
FIFO or all the blocks are read from the FIFO, it will be indicated by the
EMP bit.
When there are conditions meeting the interrupt sources, the corre-
sponding Interrupt Indication bit will be set to ‘1’ and the Interrupt Indica-
tion bit will be cleared by writing a ‘1’. A ‘1’ in the Interrupt Indication bit
means there is an interrupt. The interrupt will be reported by the INT pin
if its Interrupt Enable bit is ‘1’.
Functional Description
M[2:0]:
= 000: A valid short HDLC/SS7 packet is received, i.e., the data stream between the opening flag and the FCS is less than 32 bytes (including
32 bytes).
= 001: The current block is not the last block of the HDLC/SS7 packet.
= 010: The current block is the last block of a valid long (more than 32 bytes) HDLC/SS7 packet.
= 011: Reserved.
= 100: An invalid short HDLC/SS7 packet is received and the current block is discarded.
= 101: The current block is the last block of an invalid long HDLC/SS7 packet and the block is discarded.
= 110: Reserved.
= 111: Reserved.
The Length Indication is valid when the M2 bit is zero: Length Indication = N - 1 (N is the number of byte).
Otherwise, the Length Indication is zero.
- The data between the opening flag and the closing flag is less
- The extracted HDLC packet does not consist of an integral num-
- A 7F (Hex) abort sequence is received;
- Address is not matched if the address comparison is enabled.
The FIFO depth is 128 bytes. The FIFO is accessed by the
The interrupt sources in this block are summarized in Table 30.
bit 7
Figure 13. Overhead Indication In The FIFO
M2
M1
M0
overhead (one byte)
46
Length Indication
Table 30: Interrupt Summarize In HDLC Mode
Here the ‘C/R’ bit position is included to compare. If both bytes address
comparison is required, the high byte address position is compared with
the value in the HA[7:0] bits, or with ‘0xFC’ or ‘0xFE’. Here the ‘C/R’ bit
position is excluded to compare. And the low byte position (the byte fol-
lowing the high byte address position) is compared with the value in the
LA[7:0] bits.
discarded, but the one-byte overhead will still be written into the FIFO.
The overhead consists of the M[2:0] bits and the length indication bits as
shown in Figure 13.
to ‘1’ on the RRST bit. The reset will clear the FIFO, the PACK bit and
the EMP bit.
A block is pushed into the FIFO.
Data is still attempted to write
into the FIFO when the FIFO
has been already full (128
bytes).
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
If any of the above conditions is detected, the current block will be
The HDLC Receiver will be reset when there is a transition from ‘0’
Sources
bit 0
Interrupt Indication Bit Interrupt Enable Bit
RMBEI
OVFLI
March 22, 2004
RMBEE
OVFLE