S2062 AMCC (Applied Micro Circuits Corp), S2062 Datasheet - Page 9

• Manufacturer Part Number: S2062
• Description: Dual Serial Backplane Device
• Manufacturer: AMCC (Applied Micro Circuits Corp)

June 20, 2000 / Revision B
RECEIVER DESCRIPTION
Each receiver channel is designed to implement a
Serial Backplane receiver function through the physi-
cal layer. A block diagram showing the basic func-
tion is provided in Figure 5.
Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. After acquiring bit synchronization, the
S2062 searches the serial bit stream for the occur-
rence of a K28.5 character on which to perform word
synchronization. Once synchronization on both bit
and word boundaries is achieved, the receiver pro-
vides the decoded data on its parallel outputs.
Data Input
A differential input receiver is provided for each
channel of the S2062. Each channel has a loopback
mode in which the serial data from the transmitter
replaces external serial data. The loopback function
for both channels is controlled by the loopback en-
able signal, LPEN.
The high speed serial inputs to the S2062 are inter-
nally biased to VDD-1.3V. All that is required exter-
nally are AC-coupling and line-to-line differential
termination.
Clock Recovery Function
Clock recovery is performed on the input data
stream for each channel of the S2062. The receiver
PLL has been optimized for the anticipated needs of
Serial Backplane systems. A simple state machine in
the clock recovery macro decides whether to acquire
lock from the serial data input or from the reference
clock. The decision is based upon the frequency and
run length of the serial data inputs. If at any time the
frequency or run length checks are violated, the
state machine forces the VCO to lock to the refer-
ence clock. This allows the VCO to maintain the cor-
rect frequency in the absence of data.
Table 6. Lock to Reference Frequency Criteria
DUAL SERIAL BACKPLANE DEVICE
C
r u
U
L
e r
n
S
S
S
S
S
o
o l
a t
a t
a t
a t
a t
k c
t n
k c
e t
e t
e t
e t
e t
e
L
e
d
o
d
c
k
P
4
2
v (
v (
v (
v (
v (
L
8
4
<
8
>
<
4
>
L
. s
. s
. s
. s
. s
4
o t
7
2
o t
3
F
R
R
R
R
R
8
3
4
6
e r
E
E
E
E
E
8
7
2
4
3
6
q
F
F
F
F
F
3
6
p
p
p
p
2
6
u
C
C
C
C
C
p
p
p
p
e
L
L
L
L
L
m
p
m
m
p
m
n
p
p
K
K
K
K
K
c
m
m
)
)
)
)
)
y
N
U
U
e
w
n
n
U
U
d
d
L
L
L
n
n
t e
t e
o
o
o l
o l
o
k c
k c
r e
r e
c
k c
k c
k
m
m
e
e
e
e
d
d
S
n i
n i
d
d
a t
e
e
d
d
e t
The ‘lock to reference’ frequency criteria insure that the
S2062 will respond to variations in the serial data input
frequency (compared to the reference frequency). The
new Lock State is dependent upon the current lock
state, as shown in Table 6.
The run-length criteria insure that the S2062 will respond
appropriately and quickly to a loss of signal. The run-
length checker flags a condition of consecutive ones or
zeros across 12 parallel words. Thus 119 or less con-
secutive ones or zeros does not cause signal loss, 129
or more causes signal loss, and 120 - 128 may or may
not, depending on how the data aligns across byte
boundaries.
If both the off-frequency detect circuitry test and the run-
length test are satisfied, the CRU will attempt to lock to
the incoming data. When lock is achieved, LOCK-DET
is asserted on the ERR, EOF, and KFLAG status lines.
It is possible for the run length test to be satisfied due to
noise on the inputs, even if no signal is present. In this
case the lock detect status may periodically assert as
the VCO frequency approaches that of the REFCLK.
In any transfer of PLL control from the serial data to the
reference clock, the RCxP/N outputs remain phase con-
tinuous and glitch free, assuring the integrity of down-
stream clocking.
When operating in TCLK mode, both PLL lock status
are indicated by a 1-0-1 on the ERR, EOF, and KFLAG
outputs, respectively.
Reference Clock Input
A single reference clock, which serves both transmitter
and receiver, must be provided from a low jitter clock
source. The frequency of the received data stream (di-
vided-by-10 or -20) must be within 200 ppm of the refer-
ence clock to insure reliable locking of the receiver PLL.
Serial-to-Parallel Conversion
Once bit synchronization has been attained by the
S2062 CRU, the S2062 must synchronize to the 10
bit word boundary. Word synchronization in the
S2062 is accomplished by detecting and aligning to
the 8B/10B K28.5 codeword. The S2062 will detect
and byte-align to either polarity of the K28.5. Each
channel of the S2062 will detect and align to a K28.5
anywhere in the data stream. For TCLK or REFCLK
mode operation, the presence of a K28.5 is indicated
for each channel by the assertion of the EOFx signal.
Table 7 details the function of the EOF, KFLAG, and
ERR pins in status reporting. As indicated in Table 7,
a 1-0-1 on the ERR, EOF, and KFLAG signals on any
channel is indicative of CRU lock failure.
S2062
9