L64777 LSI Logic Corporation, L64777 Datasheet - Page 107

• Manufacturer Part Number: L64777
• Description: DVB Qam Modulator
• Manufacturer: LSI Logic Corporation

SDA
SCL
Figure A.4
A.4 Read Cycle Using the Serial Bus Interface
1
Condition
Start
2
7-bit Slave
Address
Burst Write to Slave (Master-Transmitter, Slave-Receiver)
R/W
3
SDA
(Slave)
7. The master generates another start condition.
8. The master repeats steps 2–7 to address the appropriate group and
9. The master terminates the cycle by issuing a stop condition.
Figure A.5 shows the timing for a burst, or a single read cycle. The
following cycles must take place for a read cycle:
1. The master starts the cycle by issuing a start condition.
2. The master transmits the 7-bit slave address.
3. The master sets the R/W bit = 0 to indicate a write cycle.
4. The addressed slave acknowledges the reception of the slave
5. The master sends the 8-bit Group 0 address (0x0) to indicate that
Read Cycle Using the Serial Bus Interface
ACK
4
8-bit Group
Address
write 1 or more data bytes.
address by driving SDA low in the ACK cycle.
the APR is to be loaded. (The master accesses Group 0 only to load
the APR.)
Bit 7
5
(Slave)
ACK
Bit 6
8-bit Data
Bit 5
6
(Slave)
ACK
7
Bit 4
Condition
Start
Bit 3
8
7-bit Slave
Address
Bit 2
Bit 1
(Slave)
ACK
Bit 0
8-bit Group
Address
Bit 7
(Slave)
ACK
8-bit Data
Bit 6
(Slave)
Bit 5
ACK
8-bit Data
(Slave)
ACK
9
Condition
Stop
A-5