L64777 LSI Logic Corporation, L64777 Datasheet - Page 84

• Manufacturer Part Number: L64777
• Description: DVB Qam Modulator
• Manufacturer: LSI Logic Corporation

5.3 Status Information Signals
5-4
SCLK
SSTARTIN
DIG_I[9:0]
DIG_Q[9:0]
FIFOALARM
FIRSTOUT
Signals
Modulator Symbol Clock Output
SCLK is a clock output synchronous to internally
processed symbols and bytes; it is identical to OCLK/4.
The L64777 uses SCLK to determine the phase of the
Nyquist filter output. The rising edge of SCLK is followed
by Phase 0. The falling edge is the transition of Phase 1
to Phase 2 in 4-fold oversampling mode.
Sync Sequence Start
The SSTARTIN pin is asserted to mark the beginning of
a new, fully reset sequence by a hardwired signal. The
L64777 evaluates the SSTARTIN negative slope and
restarts all internal sequences at the next Block/Frame
start following the negative SSTARTIN slope. If no
SSTARTIN is applied, all internal sequences run free
after the reset.
Digital I Component
This port provides modulator I-component output in
digital format. Depending on the PLL mode, either OCLK
or PCLK is the related clock.
Digital Q Component
This port provides modulator Q-component output in
digital format. Depending on the PLL mode, either OCLK
or PCLK is the related clock.
FIFO Collision Detected
If this alarm occurs, the FIFO control has detected equal
pointers for read and write access. A detected collision
most probably indicates unlocked external PLL-VCO
circuitry. The L64777 synchronizes this signal with
SCLK-driven flip-flops for the output.
First Block of New Sequence Out
FIRSTOUT occurs together with FSTARTOUT and
indicates the head of a sync block that has just-reset
sequences, as controlled by SSTARTIN. FIRSTOUT is
the acceptance of a SSTARTIN negative slope delayed
by all internal processing modules.
Output
Output
Output
Output
Output
Input