L64777 LSI Logic Corporation, L64777 Datasheet - Page 27
L64777
Manufacturer Part Number
L64777
Description
DVB Qam Modulator
Manufacturer
LSI Logic Corporation
Datasheet
1.L64777.pdf
(124 pages)
- Current page: 27 of 124
- Download datasheet (989Kb)
bitstream. If the microprocessor interface selects internal
synchronization, the L64777 looks for an 8-bit sync pattern S, repeated
in the DIN[0] input data stream with a given period of P bytes. For an
MPEG-2 DVB transmission, S = 0x47 and P = 204. The values S and P
are programmable in the chip to accommodate all applications based on
MPEG and MPEG-derived standards.
Parallel operation requires byte-aligning the SYNC_BYTE to achieve
data-dependant synchronization. For serial input, the L64777 searches
the SYNC_BYTE in all possible bit positions and automatically detects
the byte-alignment.
In the L64777, the sync algorithm is fixed to a procedure with
programmable values of S and P. In order to achieve the required
functionality at the lowest possible gate count, you can select from three
values of track steps, which are the number of flywheel repetitions
required to declare the states SYNCOK and loss-of-sync. There are two
phases to the sync algorithm procedure: the sync acquisition phase, and
the sync tracking phase.
2.4.1 Sync Acquisition Phase
In the sync acquisition phase, the number of sync detections required for
sync and loss is programmable from 3 to 5. TS is the designation for the
number of track steps. After TS error-free consecutive detections of the
sync byte S at the correct locations, the L64777 declares synchroniza-
tion; if a mismatch occurs, it goes back to the search state.
Validating the detection of the sync word three times ensures a
8
3
8
probability of false alarm equal to P
= (2
)
= 6*10
. Validating the
fa
detection of the sync word five times insures a probability of false alarm
8
5
13
equal to P
= (2
)
= 9*10
.
fa
Figure 2.7 shows the states occurring in the sync acquisition phase.
Figure 2.7
Sync Acquisition Phase
a0
a
a
To State S3
S0
S1
S2
b0
b
Input Synchronization
2-13
Related parts for L64777
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Mpeg-2 Audio/video Decoder
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Satellite Decoder Technical Manual 5/97
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Satellite Receiver
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Tuner/receiver Chipset
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Tuner And Satellite Receiver Chipset Data Sheet 2/01
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Smatv Qam Encoder
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Dvb-t Cofdm Demodulator Technical Manual 2/00
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
16-Bit HCMOS Multiplier / Accumulators
Manufacturer:
LSI Logic Corporation
Part Number:
Description:
Transport with Embedded CPU and Control
Manufacturer:
LSI Logic Corporation
Part Number:
Description:
32-Bit HCMOS IEEE Floating-Point Processor
Manufacturer:
LSI Logic Corporation
Part Number:
Description:
Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Variable-Length Video Shift Registers
Manufacturer:
LSI Logic Corporation