AD9510 Analog Devices, AD9510 Datasheet - Page 3

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

Preliminary Technical Data
SPECIFICATIONS
V
PLL CHARACTERISTICS
Table 1.
Parameter
REFERENCE INPUTS (REFIN)
PHASE/FREQUENCY DETECTOR (PFD)
CHARGE PUMP (CP)
RF CHARACTERISTICS
S
Input Frequency
Input Sensitivity, Differential
Input Voltage, Single-Ended
Input Common-Mode Voltage
Input Capacitance
Input Resistance
Phase Frequency Detector Input Frequency
Phase Frequency Detector Input Frequency
Phase Frequency Detector Input Frequency
Antibacklash Pulse Width
Antibacklash Pulse Width
Antibacklash Pulse Width
I
I
Sink and Source Current Matching
I
I
(CLK2 − PLL FEEDBACK)
Input Frequency
Input Sensitivity, Differential
Input Common-Mode Voltage, V
Input Single-Ended Sensitivity
Input Resistance
Input Capacitance
= 3.3 V ± 5%; V
CP
CP
CP
CP
High Value
Low Value
Absolute Accuracy
R
Sink/Source
Three-State Leakage
vs. V
vs. Temperature
SET
Range
CP
S
≤ V
CP
≤ 5.5 V, T
CM
A
= 25°C, R
Min
0
1.1
SET
= 4.12 kΩ, CPR
Typ
200
1.6
2
5
1.3
2.9
6.0
5
625
2.5
2.7/10
1
2
1.5
2
200
1.6
V
5
2
CM
± 100
Rev. PrA | Page 3 of 41
SET
= 5.1 kΩ, unless otherwise noted.
Max
250
1.7
80
1.5
Unit
MHz
mV
V
V
pF
kΩ
MHz
MHz
MHz
ns
ns
ns
mA
µA
%
kΩ
nA
%
%
%
GHz
mV
V
mV
kΩ
pF
Self-bias voltage of REFINB
Antibacklash pulse width 0D <1:0> = 00
0.5 V < CP < V
Self biased; enables ac coupling
Test Conditions/Comments
REFINB capacitively bypassed to RF ground
Antibacklash pulse width 0D <1:0> = 01
Antibacklash pulse width 0D <1:0> = 10
0D <1:0> = 00
0D <1:0> = 01
0D <1:0> = 10
Programmable
V
0.5 V < CP < V
CP = V
CLK2 is electrically identical to CLK1, the
distribution only input (see Clock Inputs); can
be used as differential or single-ended inputs
Frequencies > 800 MHz require a minimum
divide-by-2 see the Distribution section
When dc-coupled, B input capacitively
bypassed to RF ground
CP
= V
S
S
/2
/2
CP
CP
− 0.5 V
− 0.5 V
AD9510