AD9510 Analog Devices, AD9510 Datasheet - Page 40

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

AD9510
LVDS CLOCK DISTRIBUTION
Low voltage differential signaling (LVDS) is a second
differential output option for the AD9510. LVDS provides clock
signals with jitter performance nearly as good as that obtainable
from LVPECL, and better than CMOS. LVDS uses a current-
mode output stage with several user-selectable current levels. A
3.5 mA output current yields 350 mV output swing across a
standard LVDS output termination of 100 Ω, meeting ANSI 644
requirements.
A recommended termination circuit is shown for the LVDS
outputs in Figure 33.
3.3V
3.3V
LVPECL
LVDS
200Ω
Figure 31 LVPECL with Parallel Transmission Line
Figure 33. LVDS Output Termination
0.1nF
0.1nF
Figure 32. Typical LVPECL Outputs
100Ω
200Ω
differential (coupled)
differential (coupled)
100Ω
100Ω
3.3V
LVPECL
3.3V
LVDS
LVDS
Rev. PrA | Page 40 of 41
A typical LVDS output waveform is shown in Figure 34.
(See Application Note AN-586 at www.analog.com for more
information on LVDS).
POWER AND GROUNDING CONSIDERATIONS,
AND POWER SUPPLY REJECTION
Many applications seek high speed and performance under less
than ideal operating conditions. In these application circuits, the
implementation and construction of the PCB is as important as
the circuit design. Proper RF techniques must be used for device
selection, placement, and routing, as well as power supply
bypassing and grounding to ensure optimum performance.
Figure 35. Differential LC Filter for Single 3.3 V Applications
Figure 34. Typical LVDS Output Waveforms
Preliminary Technical Data