AD9510 Analog Devices, AD9510 Datasheet - Page 6

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

AD9510
Parameter
LVDS
CLK-TO-LVDS OUT
CLK-TO-LVDS OUT DELAY ADJUST CHANNEL
CMOS
CLK-TO-CMOS OUT
CLK-TO-CMOS OUT DELAY ADJUST CHANNEL
LVPECL-TO-LVDS OUT
LVPECL-TO-CMOS OUT
LVDS-TO-CMOS OUT
DELAY ADJUST
1
2
Defined as the worst-case difference between any two similar delay paths within a single device operating at the same voltage and temperature.
Defined as the absolute worst-case difference between any two delay paths on any two devices operating at the same voltage and temperature. Part-to-part skew is
the total skew difference; pin-to-pin skew + part-to-part skew.
Output Rise Time, t
Output Fall Time, t
Propagation Delay, t
Output Skew, t
Output Skew, t
Propagation Delay, t
Output Skew, t
Output Rise Time, t
Output Fall Time, t
Propagation Delay, t
Output Skew, t
Output Skew, t
Propagation Delay, t
Output Skew, t
Output Skew, t
Output Skew, t
Output Skew, t
Shortest Delay Range
Longest Delay Range
Divide = Bypass
Divide = 2 − 32
Divide = Bypass
Divide = 2 − 32
Divide = Bypass
Divide = 2 − 32
Divide = Bypass
Divide = 2 − 32
Zero Scale
Full Scale
Linearity
Zero Scale
Full Scale
Linearity
SKL
SKL_AB
SKLD
SKC
SKC_AB
SKCD
SKP_L
SKP_C
SKL_C
FL
FL
RL
RL
LVDS
LVDSD
CMOS
CMOSD
Min
Rev. PrA | Page 6 of 41
Typ
250
250
1.4
1.4
50
200
1.45
1.45
50
300
300
1.4
1.4
50
200
1.45
1.45
50
0.75
0.75
100
0.3
1.0
0.5
10
100
400
100
150
400
150
150
Max
Unit
ps
ps
ns
ns
ps
ps
ns
ns
ps
ps
ps
ns
ns
ps
ps
ns
ns
ps
ns
ns
ps
ns
ns
%LSB
ns
ns
%LSB
Test Conditions/Comments
Termination = 100 Ω differential; default
Output level setting 40 (41) (42) (43)
<2:1> = 01, 3.5 mA termination current
20% to 80%
80% to 20%
OUT4 to OUT7 on same part
LVDS on different parts
Delay off
OUT5 to OUT6 on same part
OUT5 to OUT6 on same part
B outputs are inverted; termination = open
20% to 80%; C
80% to 20%; C
C
CMOS to CMOS on same part
CMOS to CMOS on different parts
Delay off
C
OUT5 to OUT6 on same part
Everything the same; different logic
LVPECL to LVDS on same part
Everything the same; different logic
LVPECL to CMOS on same part
Everything the same; different logic
LVDS to CMOS on same part
OUT5 (OUT6); LVDS and CMOS
35h (39h) <5:0> 111111
36h (3Ah) <5:0> 000000
36h (3Ah) <5:0> 111111
35h (39h) <5:0> 000000
36h (3Ah) <5:0> 000000
36h (3Ah) <5:0> 111111
LOAD
LOAD
= 3 pF
= 3 pF
Preliminary Technical Data
LOAD
LOAD
= 3 pF
= 3 pF