AD9510 Analog Devices, AD9510 Datasheet - Page 37

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

Reg.
Addr.
(Hex)
49
(4B)
(4D)
(4F)
(51)
(53)
(55)
(57)
58
58
58
58
58
58
58
59
5A
5A
Preliminary Technical Data
Bit(s)
<7>
<0>
<1>
<2>
<3>
<4>
<6:5>
<7>
<7:0>
<0>
<7:1>
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
(OUT5)
(OUT6)
(OUT7)
Other
Pin Select
END
Name
Bypass Divider
SYNC Detect Enable
SYNC Select
Soft SYNC
Dist Ref Power Down
SYNC Power Down
FUNCTION
Update Registers
Description
Bypass and power-down divider logic; route clock directly to output (default = 0).
1 = enable SYNC detect (default = 0).
1 = raise flag if slow clocks are out-of-sync by 0.5 to 1 high speed clock cycles.
0 (default) = raise flag if slow clocks are out-of-sync by 1 to 1.5 high speed clock cycles.
Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that this bit’s
polarity is reversed. That is a High level forces selected outputs into a known state, and a High
> Low transition triggers a sync (default = 0).
1 = power-down the references for the distribution section (default = 0).
1 = power-down the SYNC (default = 0).
<6>
0
0
1
1
Reserved or not used.
Reserved or not used.
A 1 written to this bit updates all registers and transfers all serial control port register buffer
contents to the control registers on next rising SCLK edge. This is a self-clearing bit. A 0 does
not have to be written in order to clear it.
Reserved or not used.
Rev. PrA | Page 37 of 41
<5>
0
1
0
1
Function
RESETB (Default)
SYNCB
Test Only; Do Not Use
PDB
AD9510