MAX109 Maxim Integrated Products, MAX109 Datasheet - Page 13

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MAX109

Manufacturer Part Number
MAX109
Description
2.2Gsps ADC
Manufacturer
Maxim Integrated Products
Datasheet

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PIN
C14, C15, C16,
A13, A15, A17,
B14, B15, B16,
D14, D15, D16
V18, W18, Y18
NAME
W20
M20
A14
A16
B20
B19
C19
Y20
Y19
K20
PIN
M4
M3
M2
M1
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
______________________________________________________________________________________
______________________________________________________________________________________
DELGATE1
DELGATE0
SAMPADJ
CLKCOM
REFOUT
VOSADJ
NAME
REFIN
GNDR
DORN
DCOP
DCON
DORP
CLKP
CLKN
INN
INP
True/Positive Sampling Clock Input. Positive terminal for differential input configuration.
Complementary/Negative Sampling Clock Input. Negative terminal for differential input
configuration.
50Ω Clock Termination Return
Sampling Point Adjustment Input. Allows the user to adjust the sampling event by applying a
voltage between 0 to 2.5V to this input.
Timing Delay Adjustment. Coarse (MSB) adjustment for the timing between T/H amplifier and
quantizer.
Timing Delay Adjustment. Coarse (LSB) adjustment for the timing between T/H amplifier and
quantizer.
Reference Voltage Input. For applications requiring improved gain performance and reference-
voltage adjustability, allows the user to utilize the REFIN input by applying a more accurate and
adjustable reference source. This input accepts an input-voltage range of 2.5V ±10%.
Internal Reference Output. Connect to REFIN, if using the internal 2.5V bandgap reference.
Bandgap Reference Ground. Ground connection for the internal bandgap reference and its
related circuitry.
True/Positive Analog Input Terminal. For single-ended signals, apply signal to INP and reverse-
terminate INN to GNDI with a 50Ω resistor.
C om p l em entar y/N eg ati ve Anal og Inp ut Ter m i nal . For si ng l ed - end ed si g nal s, r ever se- ter m i nate IN N to
GN D I w i th a 50Ω r esi stor and ap p l y the si g nal d i r ectl y to IN P .
Analog Voltage Input to Adjust the Converter Offset. This input accepts an input-voltage range of
0 to 2.5V allowing the offset to be adjusted at roughly ±10 LSB.
True/Positive LVDS Data-Overrange Output Bit. This output flags over- and under-range
conditions of the data converter.
Complementary/Negative LVDS Data-Overrange Output Bit. This output flags over- and under-
range conditions on the data converter.
True/Positive LVDS Data Clock Output. Synchronize user-supplied data-capture board or data-
acquisition system to this clock.
Complementary/Negative LVDS Data Clock Output. Synchronize user-supplied data-capture
board or data-acquisition system to this clock.
and 1:4 Demultiplexed LVDS Outputs
FUNCTION
Pin Description (continued)
13
13

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