MAX109 Maxim Integrated Products, MAX109 Datasheet - Page 18

• Manufacturer Part Number: MAX109
• Description: 2.2Gsps ADC
• Manufacturer: Maxim Integrated Products

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The MAX109 features an on-chip 2.5V precision
bandgap reference used to generate the full-scale
range for the data converter. Connecting REFIN with
REFOUT applies the reference output to the positive
input of the reference buffer. The buffer’s negative input
is internally connected to GNDR. It is recommended
that GNDR be connected to GNDI on the user’s appli-
cation board.
If required, REFOUT can source up to 2.5mA to supply
other external devices. Additionally, an adjustable
external reference can be used to adjust the ADC’s full-
scale range. To use an external reference supply, con-
nect a high-precision bandgap reference to the REFIN
pin and leave the REFOUT pin floating. REFIN has a
typical input resistance R
input voltages of 2.5V ±10%.
The MAX109 provides data in offset binary format to
differential LVDS outputs on four output ports (PortA,
PortB, PortC, and PortD). A simplified circuit schematic
of the LVDS output cells is shown in Figure 5. All LVDS
outputs are powered from the output driver supply
V
MAX109 LVDS outputs provide a differential output-
voltage swing of 600mV
age of approximately 1.2V, and must be differentially
terminated at the far end of each transmission line pair
(true and complementary) with 100Ω.
A single differential output pair (DORP, DORN) is pro-
vided to flag an out-of-range condition, if the applied
signal is outside the allowable input range, where out-
of-range is above positive full scale (+FS) or below
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
and 1:4 Demultiplexed LVDS Outputs
Table 1. Timing Adjustments for T/H
Amplifier and Quantizer
18
DELGATE1 DELGATE0
CC
O, which can be operated at 3.3V ±10%. The
______________________________________________________________________________________
0
1
1
0
Data Out-of-Range Operation
P-P
T IM E DEL A Y
Q U A N T IZ ER
B ET WEEN
T /H A N D
REFIN
Digital LVDS Outputs
with a common-mode volt-
25ps
50ps
Internal Reference
of 5kΩ and accepts
(DORP, DORN)
RECOMMENDED
f
to 2.5Gsps
f
to 2.2Gsps
CLK
CLK
FOR CLOCK
SPEEDS OF
= 2.2Gsps
= 1.75Gsps
negative full scale (-FS). The DORP/DORN transitions
high/low whenever any of the four output ports (PortA,
PortB, PortC, and PortD) display out-of-range data.
DORP/DORN features the same latency as the ADC
output data and is demultiplexed in a similar fashion, so
that this out-of-range signal and the data samples are
time-aligned.
The MAX109’s internal 1:4 demultiplexer spreads the
ADC core’s 8-bit data across 32 true LVDS outputs and
allows for easy data capture in three different modes.
Two TTL/CMOS-compatible inputs are utilized to create
the different modes: SDR (standard data rate), DDR
Figure 5. Simplified LVDS Output Circuitry
Table 2. Data Rate Selection for
Demultiplexer Operation
X = Do not care.
DDR QDR
0
1
1
X
0
1
SDR mode, PortA, PortB, PortC, and
PortD enabled, 550Msps per port
DDR mode, PortA, PortB, PortC, and
PortD enabled, 550Msps per port
QDR mode, PortA, PortB, PortC, and
PortD enabled, 550Msps per port
DEMULTIPLEXER OPERATION
CMFB
Demultiplexer Operation
CMFB:
COMMON-MODE
FEEDBACK
V
CC
O
GNDO
V
CC
O
GNDO
AOP–A7P
BOP–B7P
COP–C7P
DOP–D7P
DCOP
RSTOUTP
AON–A7N
BON–B7N
CON–C7N
DON–D7N
DCON
RSTOUTN
f
SPEED
f
f
C LK
CLK
CLK
DCO
/ 16
/ 4
/ 8