MAX109 Maxim Integrated Products, MAX109 Datasheet - Page 22

• Manufacturer Part Number: MAX109
• Description: 2.2Gsps ADC
• Manufacturer: Maxim Integrated Products

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8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
and 1:4 Demultiplexed LVDS Outputs
Table 4. Digital Output Codes Corresponding to a DC-Coupled
Single-Ended Analog Input
Table 5. Digital Output Codes Corresponding to a DC-Coupled Differential Analog Input
Table 6. Driving Options for DC-Coupled Clock
Table 7. Demultiplexer and Reset Operations
ble input drive requirements. Each clock input is termi-
nated with an on-chip, laser-trimmed 50Ω resistor to
CLKCOM (clock-termination return). The CLKCOM ter-
mination voltage can be connected anywhere between
ground and -2V for compatibility with standard-ECL drive
levels. The clock inputs are internally buffered with a pre-
amplifier to ensure proper operation of the data convert-
er, even with small-amplitude sine-wave sources. The
MAX109 was designed for single-ended, low-phase
22
Single-ended sine wave
Differential sine wave
Single-ended ECL
Differential ECL
CLKP/CLKN
DCOP/DCON
RSTINP/RSTINN
RSTOUTP/RSTOUTN
IN-PHASE/TRUE INPUT
SIGNAL/PIN NAME
IN-PHASE/TRUE INPUT
______________________________________________________________________________________
-125mV + 0.5 LSB
125mV - 0.5 LSB
-250mV + 1 LSB
250mV - 1 LSB
CLOCK DRIVE
<-125mV
<-250mV
-125mV
-250mV
125mV
250mV
(INP)
(INP)
0
0
Sampling clock inputs
LVDS outputs
LVDS inputs
LVDS outputs
-10dBm to +15dBm
-10dBm to +10dBm
INVERTED/COMPLEMENTARY
INVERTED/COMPLEMENTARY
TYPE
ECL drive
ECL drive
CLKP
-125mV + 0.5 LSB
125mV - 0.5 LSB
INPUT (INN)
INPUT (INN)
>+125mV
-125mV
125mV
0
0
0
0
0
0
0
Master ADC timing signal. The ADC samples on the rising edge of CLKP.
Data clock output (LVDS). Output data changes on the rising edge of DCOP.
D em ul ti p l exer r eset i np ut si g nal s. Resets the i nter nal d em ul ti p l exer w hen asser ted .
Reset outputs for synchronizing the resets of multiple external devices.
Externally terminated to GNDI with 50Ω
-10dBm to +10dBm
noise sine-wave clock signals with as little as 100mV
amplitude (-10dBm), thereby eliminating the need for an
external ECL clock buffer and its added jitter.
Excellent performance is obtained by AC- or DC-cou-
pling a low-phase-noise sine-wave source into a single
clock input (Figure 13a, Table 6). For proper DC bal-
ance, the undriven clock input should be externally
ECL drive
CLKN
-1.3V
OUT-OF-RANGE BIT
OUT-OF-RANGE BIT
(DORP/DORN)
(DORP/DORN)
FUNCTIONAL DESCRIPTION
Single-Ended Clock Inputs (Sine-Wave Drive)
1
0
0
0
0
1
1
0
0
0
0
1
11111111 (full scale)
11111111
10000000 toggles 01111111
00000001
00000000 (zero scale)
00000000 (out of range)
11111111 (full scale)
11111111
10000000 toggles 01111111
00000001
00000000 (zero scale)
00000000 (out of range)
CLKCOM
GNDI
GNDI
-2V
-2V
OUTPUT CODE
OUTPUT CODE
REFERENCE
Figure 13a
Figure 13b
Figure 13c
Figure 13d