MAX109 Maxim Integrated Products, MAX109 Datasheet - Page 20

• Manufacturer Part Number: MAX109
• Description: 2.2Gsps ADC
• Manufacturer: Maxim Integrated Products

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8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
and 1:4 Demultiplexed LVDS Outputs
Figure 7. Timing Diagram for DDR Mode, f CLK / 8 Mode
Figure 8. Timing Diagram for QDR Mode, f CLK / 16 Mode
20
PORTC DATA
PORTC DATA
PORTD DATA
PORTD DATA
PORTA DATA
PORTB DATA
PORTA DATA
PORTB DATA
DCON
DCON
CLKN
DCOP
CLKN
DCOP
CLKP
______________________________________________________________________________________
CLKP
NOTE: THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B
PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND
PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK.
NOTE: THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B
PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND
PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK.
N
N
ADC SAMPLE NUMBER
ADC SAMPLE NUMBER
N + 1 N + 2 N + 3
N + 1 N + 2 N + 3
N + 4
N + 4
N + 5
N + 5
ADC SAMPLES ON THE RISING EDGE OF CLKP
ADC SAMPLES ON THE RISING EDGE OF CLKP
N + 6 N + 7
N + 6 N + 7
FROM DLL IN FPGA
N + 8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19
N + 8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19
N
N
SAMPLE HERE
SAMPLE HERE
N + 1
N + 2
N + 3
N + 4
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 8
N + 5
N + 6
N + 7
N + 8
t
t
t
t
PD2QDR
PD2DDR
PD1QDR
PD1DDR