MAX109 Maxim Integrated Products, MAX109 Datasheet - Page 17

• Manufacturer Part Number: MAX109
• Description: 2.2Gsps ADC
• Manufacturer: Maxim Integrated Products

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Aperture width, delay, and jitter are parameters that
affect the dynamic performance of high-speed convert-
ers. Aperture jitter, in particular, directly influences SNR
and limits the maximum slew rate (dV/dt) that can be
digitized without contributing significant errors. The
MAX109’s innovative T/H amplifier design limits aper-
ture jitter typically to 0.2ps.
Figure 3. Internal Structure of the 3.2GHz T/H Amplifier
Figure 4. T/H Aperture Timing
CLKCOM
SIMPLIFIED DIAGRAM
(INPUT ESD PROTECTION
NOT SHOWN).
CLKP
CLKN
INN
INP
50Ω
50Ω
DATA (T/H)
SAMPLED
ANALOG
GNDI
INPUT
CLKN
CLKP
T/H
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
t
AD
50Ω
50Ω
TRACK
______________________________________________________________________________________
AMPLIFIER
SPLITTER
CLOCK
INPUT
APERTURE DELAY (t
APERTURE WIDTH (t
APERTURE JITTER (t
T/H
t
t
HOLD
AW
AJ
and 1:4 Demultiplexed LVDS Outputs
GNDI
AD
AJ
AW
AMPLIFIER
C
)
BUFFER
)
TO
COMPARATORS
)
HOLD
TRACK
TO
COMPARATORS
Aperture width (t
to disconnect the hold capacitor from the input circuit
(e.g., to turn off the sampling bridge and put the T/H
unit in hold mode). Aperture jitter (t
sample variation in the time between the samples.
Aperture delay (t
rising edge of the sampling clock and the instant when
an actual sample event is occurring (Figure 4).
The MAX109 clock signals are terminated with 50Ω to
the CLKCOM pin. The clock system provides clock sig-
nals, T/H amplifier, quantizer, and all back-end digital
blocks. The MAX109 also produces a digitized output
clock for synchronization with external FPGA or data-
capture devices. Note that there is a 1.6ns delay
between the clock input (CLKP/CLKN) and its digitized
output representation (DCOP/DCON).
The proper sampling point can be adjusted by utilizing
SAMPADJ as the control line. SAMPADJ accepts an
input-voltage range of 0 to 2.5V, correlating with up to
32ps timing adjustment. The nominal open-circuit volt-
age corresponds to the minimum sampling delay. With
an input resistance R
pin can be adjusted externally with a 10kΩ potentiome-
ter connected between REFOUT and GNDI to adjust for
the proper sampling point.
Another important feature of the MAX109, is the selec-
tion of the proper quantizer capture point between the
T/H amplifier and the ADC core. Depending on the
selected sampling speed for the application, two con-
trol lines can be utilized to set the proper capture point
between these two circuits. DELGATE0 (LSB) and DEL-
GATE1 (MSB) set the coarse timing of the proper cap-
ture point. Using these control lines allow the user to
adjust the time after which the quantizer latches held
data from the T/H amplifier between 25ps and 50ps
(Table 1). This timing feature enables the MAX109 T/H
amplifier to settle its output properly before the quantiz-
er captures and digitizes the data, thereby achieving
the best dynamic performance for any application.
Aperture Width, Aperture Jitter, and Aperture Delay
T/H Amplifier to Quantizer Capture Point
Sampling Point Adjustment (SAMPADJ)
Adjustment (DELGATE0, DELGATE1)
AW
AD
) is the time the T/H circuit requires
) is the time defined between the
SAMPADJ
of typically 50kΩ, this
AJ
) is the sample-to-
Clock System
17